Mitch Bailey
10/19/2021, 12:35 AMsky130_fd_io.spice
file.
* Modified by Tim: The resistors here are in an annular shape, and they overlap
* between cells such that the center of the resistor connects between the two
* devices. To be correct, these two nets must come out as pins.
.SUBCKT sky130_fd_io__signal_5_sym_hv_local_5term GATE IN NBODY NWELLRING VGND net16
*.PININFO GATE:I IN:B NBODY:B NWELLRING:B VGND:B
XI1 IN GATE VGND NBODY sky130_fd_pr__esd_nfet_g5v0d10v5 m=1 w=5.4 l=0.6 mult=1
+ sa=0.0 sb=0.0 sd=0.0 topography=normal area=0.048 perim=0.94
* RI9 net18 NBODY short
* RI8 net16 NWELLRING short
RI9 net18 NBODY sky130_fd_pr__res_generic_m1
RI8 net16 NWELLRING sky130_fd_pr__res_generic_m1
.ENDS sky130_fd_io__signal_5_sym_hv_local_5term
Looks like you (or some other Tim) added net16
to the pin list.
Two of the calling subcircuits, sky130_fd_io__gpio_buf_localesd
and sky130_fd_io__gpio_buf_localesd
, have also been modified, but looks like there was one more.
.SUBCKT sky130_fd_io__gpio_ovtv2_hotswap_pghs_i2c_fix EN_H FORCE_H[1] OD_I_H_N
+ P3OUT PAD PADLO PGHS_H TIE_HI VCC_IO_SOFT VDDIO VPB_DRVR VPWR_KA VSSD
*.PININFO EN_H:I FORCE_H[1]:I OD_I_H_N:I P3OUT:O PAD:I PADLO:O
*.PININFO PGHS_H:O TIE_HI:I VCC_IO_SOFT:I VDDIO:I VPB_DRVR:I VPWR_KA:I
*.PININFO VSSD:I
Xhsctl_q0 EN_H enhs_lat_h_n FORCE_H[1] OD_I_H_N P3OUT PAD net50 VDDIO VPB_DRVR
+ VPWR_KA VSSD sky130_fd_io__gpio_ovtv2_hotswap_ctl_i2c_fix
XI3 enhs_latbuf_h_n PADLO sky130_fd_io__sio_tk_em1s
XEpghs12 PGHS_H net54 sky130_fd_io__sio_tk_em1o
XI2 enhs_lat_h enhs_latbuf_h_n VSSD VSSD VDDIO VDDIO
+ sky130_fd_io__sio_hvsbt_inv_x4
XI1 enhs_lat_h_n enhs_lat_h VSSD VSSD VDDIO VDDIO sky130_fd_io__sio_hvsbt_inv_x1
Xpghspu_q0 PAD PGHS_H net50 TIE_HI VCC_IO_SOFT VPB_DRVR
+ sky130_fd_io__gpio_ovtv2_hotswap_pghspu
Xclamp_q0 VSSD VDDIO VSSD VDDIO PAD sky130_fd_io__signal_5_sym_hv_local_5term
* =========================================
Xpghs12_q0 net54 PADLO VPB_DRVR VPB_DRVR sky130_fd_pr__pfet_g5v0d10v5 m=1 w=3.0
+ l=1.0 mult=1 sa=0.265 sb=0.265 sd=0.28 topography=normal area=0.063 perim=1.14
.ENDS sky130_fd_io__gpio_ovtv2_hotswap_pghs_i2c_fix
I think it's sufficient to add a VDDIO
connection after PAD
. Maybe it's not used in caravel, though.Tim Edwards
10/19/2021, 12:57 AMgpiov2
but probably I missed the one in gpio_ovtv2
because it's not used in Caravel. Question: It's not used in Caravel, so why is it showing up in your LVS results?Mitch Bailey
10/19/2021, 1:01 AMsky130_fd_io__signal_5_sym_hv_local_5term
extracted layout, but I can't see the 68/13 layer in klayout.Tim Edwards
10/19/2021, 1:04 AMTim Edwards
10/19/2021, 1:05 AMMitch Bailey
10/19/2021, 1:19 AMchip_io
gds of the caravel repo 40f091a8
. I see 68/15 in the nearby sky130_fd_io__res250only___small
but neither 68/13 or 68/13 in sky130_fd_io__signal_5_sym_hv_local_5term
.
Could magic be calculating "m1 resistor" or "m1 short" from other layers on gdsin?Tim Edwards
10/19/2021, 1:50 AMMitch Bailey
10/19/2021, 2:50 AMFlattenUnmatched
function, around 3441 in netcmp.c
(gdb) p ob
$33 = (struct objlist *) 0x31796b732f30715f
(gdb) p *tc
$30 = {
file = 1,
name = 0x19dc5860 "sky130_fd_io__gpiov2_odrvr",
number = 1,
dumped = 0,
flags = 130 '\202',
class = 0 '\000',
classhash = 15982189494909831418,
permutes = 0x0,
cell = 0x19dd1410,
objdict = {
hashsize = 42073,
hashfirstindex = 0,
hashfirstptr = 0x0,
hashtab = 0x1a8f3d80
},
instdict = {
hashsize = 42073,
hashfirstindex = 0,
hashfirstptr = 0x0,
hashtab = 0x1a946070
},
propdict = {
hashsize = 42073,
hashfirstindex = 0,
hashfirstptr = 0x0,
hashtab = 0x1a998360
},
nodename_cache = 0x19ddf750,
nodename_cache_maxnodenum = 16,
embedding = 0x0,
next = 0x0
}
(gdb) p tcsub
$5 = (struct nlist *) 0x0
I checked the cell pointer list and it appears to end in a NULL, so I'm thinking ob
must be getting overwritten somewhere.
(gdb) p *(tc->cell->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next->next)
$35 = {
name = 0x19dd6720 "sky130_fd_io__com_padbondpad_q0/VGND_IO",
type = 2,
model = {
class = 0x19dd66e0 "sky130_fd_io__com_pad",
port = 433940192
},
instance = {
name = 0x19dd66a0 "sky130_fd_io__com_padbondpad_q0",
props = 0x19dd66a0
},
flags = 0 '\000',
node = 16,
next = 0x0
}
Mitch Bailey
10/20/2021, 1:28 AMFlattenUnmatched
from netcmp.c
with some debug statements I added
Fprintf(stdout, "DEBUG: FlattenUnmatched recursing\n");
changed = 1;
struct objlist * next_ob = tc->cell;
while (changed) {
changed = 0;
for (ob = tc->cell; ob != NULL; ob = ob->next) {
next_ob = ob->next;
tcsub = NULL;
if (ob->type == FIRSTPIN) {
/* First check if there is a class equivalent */
tcsub = LookupCellFile(ob->model.class, tc->file);
if (!tcsub || (tcsub->class != CLASS_SUBCKT)) continue;
else if (tcsub == tc) continue;
if (FlattenUnmatched(tcsub, tc->name, stoplevel, loclevel + 1)) {
changed = 1;
break;
}
}
if (next_ob != ob->next) {
Fprintf(stdout, "DEBUG2: %p %p %d\n", (void *) next_ob, (void *) ob->next, ob->type);
Fprintf(stdout, "DEBUG2: ob overwrite %s\n", ob->model.class);
}
}
}
Fprintf(stdout, "DEBUG: FlattenUnmatched done %d\n", loclevel);
I added the DEBUG2
statements to see if the next pointer unexpectedly changed after recursing. Unfortunately, it does. Looking for a solution now.Mitch Bailey
10/26/2021, 2:16 AMflow.tcl
or caravel/Makefile
will only check the top level of the gate level verilog. Undefined cells are treated as blackboxes with only the pins being checked. This may be ok if each level is hardened, verified separately, and placed as a macro, but otherwise how are the sub-hierarchies verified?Rahul Bharadwaj
10/27/2021, 11:43 AMRahul Bharadwaj
11/02/2021, 8:10 AMMitch Bailey
11/11/2021, 5:32 PMisosub
to layout imported from GDS? Calibre allows you to add layers to individual cells in the rule file, but that's not possible in magic, is it? I'm trying to avoid having to recreate the gds with the isosub
layer. i was thinking that if the mag
files were around, one could relatively easily add the isosub
layers there, but it looks like the extraction script for gds doesn't use/keep mag
files.Jorge Marin
12/29/2021, 4:29 PMMitch Bailey
01/05/2022, 3:05 PMchip_io
block, I'm flattening all the subcells for sky130_ef_io__vssio_hvc_clamped_pad
with gds flatglob
before extracting. Looking at the layout, it seems to me that VSSIO
is shorted to VSSIO_Q
, but there is no message in the extraction log. VSSIO_Q
is missing from the spice file.
The layout has labels on met5/label (72/5)
and rectangles and labels on met5/pin (72/16)
. The ext
file has both VSSIO
and VSSIO_Q
ports that are merged but not directly. There are several intermediate nodes. Is this why there is no warning message?
Also, how are the labels and pins extracted? Are labels from both the pin
and the label
layers valid? Will a met5/label
on a met5/pin
give a valid port?Mitch Bailey
01/05/2022, 3:08 PMTim Edwards
01/05/2022, 6:16 PMJanani Aravind
01/25/2022, 1:32 PMAnton Blanchard
01/26/2022, 11:53 PMMAGIC_EXT_USE_GDS=1
). I had to make a small fix to openlane so it would read from the gds.spice (vs lef.spice), but I'm now stuck because CVC can't find models for the pfet/nfets. I see some pretty detailed spice modules in the PDK, but CVC doesn't seem to like them (is the CDL format a subset of the spice format?). Also not sure if those models are overkill for this.Mitch Bailey
02/09/2022, 6:39 AMext
file indicate a problem with substrate extraction or is this the default no connection state?
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Noah Moroze
03/04/2022, 9:19 PMMitch Bailey
03/06/2022, 5:51 PMMitch Bailey
03/09/2022, 6:00 AMsconnect_for_sky130_magic
with all the necessary files and scripts.Mitch Bailey
03/10/2022, 4:28 AMrun_scheck <top_cell> <gds_file>
without any other settings. Feedback is appreciated.
https://github.com/d-m-bailey/sconnect_for_sky130_magicMitch Bailey
04/07/2022, 6:06 AMslot-037
is the skull inverter. The inverter input is A
and has an li
pin. However, the parent hierarchy does not connect with li
but rather drops mcon
directly on the pin. The actual layout should be connected, but the extracted netlist does not appear to be.
.subckt skullfet_inverter Y A VPWR VGND
X0 Y A VPWR VPWR sky130_fd_pr__pfet_01v8 ad=6.2694e+12p pd=2.664e+07u as=4.4307e+12p ps=1.09e+07u w=4.05e+06u l=400000u
X1 VGND A Y VGND sky130_fd_pr__nfet_01v8 ad=4.2687e+12p pd=1.082e+07u as=6.4314e+12p ps=2.672e+07u w=4.05e+06u l=400000u
.ends
.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
...
Xskullfet_inverter_0 io_analog[1] skullfet_inverter_0/A vdda1_uq1 vssa1_uq1 skullfet_inverter
.ends
@UserAnton Blanchard
04/14/2022, 12:41 AMJanani Aravind
05/19/2022, 12:42 AMMitch Bailey
07/14/2022, 6:33 AMuser_project_wrapper
and want to check the connections. Currently, magic optimizes out empty cells when netlisting.Paul Toth
01/01/2023, 5:41 AMMatt Liberty
04/13/2023, 11:18 PM