@User: Possibly netgen is just unhappy about the substrate connection. The abstracted views of the pad cells mean that the substrate gets extracted as a floating net for the top level and the digital core; the core verilog/schematic netlist has no substrate pin. This can be a pain to deal with when using abstracted views in magic. You may just need to remove the VSUBS references from the layout-extracted netlist. I will look at the issue with the

elements

command in netgen. By the way, HLD_H_N and all signals ending in _H are 3.3V signals and should not be connected to 1.8V digital logic except through a level-shifter (such as the level shifter buffer in the HVL logic library).

Ah got it, thanks for taking a look and for the heads up RE: logic levels. That’s a good thought, I just tried removing the VSUBS references from the extracted SPICE layout and rerunning LVS - I get one less error now, the net mismatch between VSUBS and proxyVSUBS is gone but the others remain