@User: We do not have a crystal oscillator or RC oscillator design, so any input clock will have to be provided by an external CMOS (or similar) clock generator. I have a "quick hack" digital frequency-locked loop design that is probably good for digital that is not too sensitive to phase noise. We do not have a true PLL design with a steady VCO, so if you do anything that is cycle-to-cycle phase noise sensitive, it will have to be piped in from outside, which means probably < 20MHz if you want a reliable full swing rail-to-rail signal. We will of course be very happy to see anyone submitting a design for a crystal oscillator, RC oscillator, VCO, PLL, or high-speed I/O drivers.

I started to sketch crystal oscillator designs. Irritatingly what I thought were obvious approaches have active patents. I presume we want to aim for things without IP encumberments?