Hello all! I need help in post- layout simulation of my design using sky130. If anyone could provide me some learning resources for that. @User @User

For digital designs, there is now a tool Open RCX that generates an SDF timing file that can be back-annotated into a simulation. Unfortunately, iverilog does not support SDF annotation. There is a tool called CVC here: http://www.tachyon-da.com/what-is-cvc/ that will simulate with parasitics. This solution has the complication that the verilog files for the standard cells need to be remade with the "specify" sections included (I created a script for this that can be enabled in open_pdks). Also IRSIM is a choice: http://opencircuitdesign.com/irsim will simulate a digital design with parasitics extracted from Magic, but because it is a transistor-level switch simulator, it runs maybe 10 to 100 times slower than a verilog simulator. But I've been able to run short programs on the Caravel microcontroller in IRSIM. That method has a complication that magic's .sim file output is now incompatible with IRSIM so I had to write a script to convert magic's output back into something that IRSIM can read. I will update IRSIM some time soon to read magic's output.

Thank you! @Tim Edwards. One thing more if you could provide resource for spice extraction and simulation.

@Tim Edwards In the OpenRCX git repo (archived) I don't see any information about generating SDF files. Could you please help me?