open-source-silicon.dev

Hello all! 
Can anyone provide me the information about the following.
1) maximum operating frequency of caravel soc.
2) how many cycles logic analyzer takes for read/write operations.
3) what is the maximum frequency available for user project area.

good questions. I'll have a go but these are estimates from my own experience.

1: the clock input we expect to be about 10mhz, but with the DLL we can get a higher caravel clock. We expect about 50Mhz max clock for caravel

2: quite a lot, it's pinned to picorv32 which executes out of flash. I have tested this but lost the results somewhere. Its in the order of 10s to 100s of cycles

3: that is down to what your design is and what you want to do with it. You should be able to get a second clock from the dll at much higher frequencies, maybe up to 500mhz, but you will be limited by the IO at about 50mhz.

Thank you <@U0172QZ342D>!
1: So 50MHz max is not an actual maximum operating frequency for Caravel but an estimate?? 
2: In short read/write from LA is not a single cycle operation??

1: yes. A very similar design was used on strive, so maybe <@U016EM8L91B> could give you some information about whether they tested it to find max freq.

2: no, definitely not single cycle. Let me just see if I have a test bench handy.

run the la_test1 example and add a few more writes to the logic analyser

Alright thank you! 
Let me see in detail.

<@U01GT28LLSE>:  50MHz was what the SoC core of caravel was synthesized to.  The actual clock on the development board runs at 10MHz.  The user project can get clocked from the secondary DLL clock, as Matt mentioned, but his number was high;  the upper bound on that clock will be something like 150MHz (anything higher is pretty unrealistic for something synthesized in a 130nm process).  The picoRV32 is not pipelined, so instructions are 4 cycles, sequential, and so your maximum rate for reading over the logic analyzer interface would be maybe 20 clock cycles for a read, write, increment, test, and loop.  To get that rate, though, you would need to copy the routine into memory and switch program execution from the SPI flash to SRAM.  That is the only way to avoid getting slowed down by the SPI flash access delay.

Thank you <@U016EM8L91B>! 
So we can use upto 150MHz in user area right?? But the limitations of 10MHz is due to the management soc and IO pads. If I am not wrong?

10MHz is just a choice for the board.  The GPIO pad input frequency limit is 60MHz according to the SkyWater I/O specification.  The management SoC design is limited to 50MHz, although that's under worst-case conditions, so in normal conditions (e.g., room temperature) you can probably overclock it.

Alright thank you for your kind response!