@User Here's a test case. It seems older versions of netgen (1.5.159) were fine with an extra port, but newer ones (1.5.219) are not. Magic (8.3.260) extracts an extra port in a my write_driver cell for an unapparent reason...

Subcircuit pins:
Circuit 1: write_driver                    |Circuit 2: write_driver                    
-------------------------------------------|-------------------------------------------
bl                                         |bl                                         
br                                         |br                                         
gnd                                        |gnd                                        
din                                        |din                                        
en                                         |en                                         
vdd                                        |vdd                                        
w_n12_552#                                 |(no matching pin)                          
---------------------------------------------------------------------------------------

but this port is actually not connected to anything. At the next level up, it gets connected to gnd. The extracted netlist is port_data.spice.

@User This would be just a temporary solution, but I have a version of netgen that flattens circuits with unmatched ports instead of creating proxy ports. The mpw-4

sky130_sram_1kbyte_1rw1r_32x256_8

and

sky130_sram_2kbyte_1rw1r_32x512_8

pass LVS. If you're interested, I'll post it to github (with the standard OSS warranty - i.e. use at your own risk).

@User Right now, I can seem to use an old version of netgen. I already had all the macros passing LVS in mpw-4...