I'm currently trying to do LVS. I have subcells where I use a deep nwell under NMOS transistors so I can connect the bulk to something else than GND. I find however that in the netlist, the bulk is connected wrongly. Here is a sample that demonstrates the behaviour. The transistors top and left (see attached image) have the nwell in the top cell, while the one at the lower right corner has the nwell in the subcell. The Result in the spice file looks as follows:

X0 D2 G2 S2 B2 sky130_fd_pr__nfet_01v8 [..]
X1 D G S B sky130_fd_pr__nfet_01v8 [..]
X2 s3 g3 d3 b3 sky130_fd_pr__nfet_01v8_lvt [..]
X3 d3 g3 s3 b3 sky130_fd_pr__nfet_01v8_lvt [..]
X4 isource_diffamp_0/S isource_diffamp_0/G isource_diffamp_0/D B2 sky130_fd_pr__nfet_01v8_lvt [..]
...

For X4 I get B2 as the bulk connection but it should be isource_diffamp_0/B I guess I should file a bug report. Any ideas for a workaround?

Which version of magic? Some versions had this issue.

I'm using the current master from git

Thank you @User! For the given example that works. If I apply what you proposed to my design the issue with the bulk is solved, but I get now label names that look like the following:

Topmost cell in the window/VM22D

Spice uses spaces as seaparators so the spice file is invalid. In the spice file things now look like:

X53 Topmost cell in the window/VM22D a_216_n2258# Topmost cell in the window/VM3D isource_out_0/VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=4e+06u l=6e+06u

What seems to improve the situation is to only select the cells that contain non-grounded bulk and do

select flat ; select keep

After this step I have to delete all labels that were contained in the subcell.