and also sv2v if you want to use full systemverilog

betwen iverilog (icarus verlog right ? ) and verilator which one is better. I have used so far modelsim for my VHDL simulations.

They have 2 different paradigms - icarus verilog lets you write your testbenches in non-synthesizable verilog (which lets you use wait/delay statements), while verilator converts your verilog into a C++ class, which you instantiate and then testbench in C++ or Python ( timing is usually controlled with a small

tick

function that ticks the clock, advances time, and saves waveforms)

With respect to these two paradigms, what are the advantages w.r.t simple designs and more developed designs.