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I use icarus verilog simulator. In a counter design, the counter counts with rising edge clock . So at each  rising edge there is a new value of the counter register. When I run simulation for long time, I see a shift in the clock as if the counter value changes after rising edge with a certain time. Any one knows the cause of this ? Thanks

posting your testbench code or a screenshot of the waveform in question would help provide context

20200906_145558.png

<@U019Q0F3H0A> thanks for the waveform screenshot. I see the behavior you're describing but I have no idea why from just the waveform. If you are able to post your testbench file that produces the clocks, that may show something in the modeling code.

<@U018F616ZTL>  I really appreciate your care. I have a clock generator module contains the below code. This module is connected to the DUT in the testbench feeds it with clocks. 

always 
        begin
                  #(DDR_CLK_PERIOD/2) TxDDRClkHS_reg = ~TxDDRClkHS_reg;
        end

always 
        begin
#(BYTE_CLKHS_PERIOD/2) TxByteClkHS_reg = ~TxByteClkHS_reg;
       
        end

always 
        begin

   #(BYTE_CLK_PERIOD/2) 
TxByteClk_reg = ~TxByteClk_reg;
        end

//outputs
assign TxDDRClkHS  =  TxDDRClkHS_reg;
assign TxByteClkHS =  TxByteClkHS_reg;
assign TxByteClk   =  TxByteClk_reg;

At the begining I define the timescale and some parameters. 

'timescale 1ns/1ps

parameter DDR_CLK_PERIOD =1.01

parameter BYTE_CLK_PERIOD =3

parameter BYTE_CLKHS_PERIOD =4

I think it can be solved if the slowest one is derived from the fastest. 

I will try it today.

Thanks

````timescale 1ns/1ps

module top();
parameter DDR_CLK_PERIOD =1.01;
parameter BYTE_CLK_PERIOD =3;
parameter BYTE_CLKHS_PERIOD =4;

reg TxDDRClkHS_reg =0;
reg TxByteClk_reg = 0;
reg TxByteClkHS_reg = 0;

initial begin
	forever begin
        	#(DDR_CLK_PERIOD/2) TxDDRClkHS_reg = ~TxDDRClkHS_reg;
        end
end
initial begin
	forever begin
		#(BYTE_CLKHS_PERIOD/2) TxByteClkHS_reg = ~TxByteClkHS_reg;
        end
end
always
        begin
   #(BYTE_CLK_PERIOD/2)
TxByteClk_reg = ~TxByteClk_reg;
        end
//outputs
wire TxDDRClkHS  =  TxDDRClkHS_reg;
wire TxByteClkHS =  TxByteClkHS_reg;
wire TxByteClk   =  TxByteClk_reg; 

initial begin
	$dumpfile("test.vcd");
	$dumpvars;
end

endmodule```

that's what I wrote up to simulate what you provided, but yes, I think you're correct

the problem that youv'e described is the clocks drifting in relation to one another and as you've shown in the parameters that describe the clock periods, the clocks are unrelated

so great job, you solved your own problem

Thanks Russell. It works fine now. Counter is always zero with every new byte when I divide the DDR Clock by 4.