Hi all, what should I do to eliminate setup violations?

[ERROR]: There are setup violations in the design at the typical corner. Please refer to 'designs/mydesigns/VLSI-Workshop/Adders/runs/RUN_2022.07.12_19.28.51/reports/signoff/28-rcx_sta.max.rpt'.

My config.tcl :

# User config

set ::env(DESIGN_NAME) ripple_carry

# Change if needed

set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/ripple_carry.v]

# Fill this

set ::env(CLOCK_PERIOD) "10.0"

set ::env(CLOCK_PORT) ""

set ::env(PL_TARGET_DENSITY) 0.7

set ::env(CELL_PAD) 2

set ::env(DIE_AREA) "0 0 400 400"

set ::env(FP_SIZING) absolute

set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) 100

set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1

set ::env(FP_CORE_UTIL) 30

set ::env(PL_BASIC_PLACEMENT) 0

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl

if { [file exists $filename] == 1} {

source $filename

}