I suppose if the counter starts up at some random value then as you say the phase will be unknown but it will start up ok

Right, it's a simulation thing only, the real design will just settle on either 0 or 1 for each FF.

Exactly. In simulation if the counter starts at XXX then on the next clock it will be XXX+1 which is also XXX. In the real circuit it might start at 26, and then the next clock it will be 26+1 which is 27 and that is good enough in practice

That is not true for all designs, of course. It might be that the counter should never be more than, for example, 110. Having it start out at 121 could be really bad

thanks both!

Hello all, is there anyway to simulate VHDL and Verilog designs together. I have my designs in Verilog but test gen in VHDL.

Hello everyone, I am trying to do pre synthesis simulation and post synthesis simulation of 8 bit counter. And using tools For simulation iverilog For synthesis yosys and standard cells verilog models from sky130 I am getting perfect results for pre synthesis simulation. But when I am trying to do post synthesis simulation output is 'x' The following is the link where I have kept in three folders 1. pre-synthesis simulation, which I am getting 2. synthesis folder where i have done synthesis using yosys 3. post-synthesis simulation, which I am not getting https://drive.google.com/file/d/1iVb8iZ85-nPuvsS5HyK-0hpmGh9dteSx/view?usp=sharing Please help.

Problem solved, it was this: https://github.com/google/skywater-pdk/issues/310

Hi All, Is anyone able to pass verification post synth (+sdf) or post apr (+back annotation)? @User @User It would great to check here.

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Hi all, what should I do to eliminate setup violations?

[ERROR]: There are setup violations in the design at the typical corner. Please refer to 'designs/mydesigns/VLSI-Workshop/Adders/runs/RUN_2022.07.12_19.28.51/reports/signoff/28-rcx_sta.max.rpt'.

My config.tcl :

# User config

set ::env(DESIGN_NAME) ripple_carry

# Change if needed

set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/ripple_carry.v]

# Fill this

set ::env(CLOCK_PERIOD) "10.0"

set ::env(CLOCK_PORT) ""

set ::env(PL_TARGET_DENSITY) 0.7

set ::env(CELL_PAD) 2

set ::env(DIE_AREA) "0 0 400 400"

set ::env(FP_SIZING) absolute

set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) 100

set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1

set ::env(FP_CORE_UTIL) 30

set ::env(PL_BASIC_PLACEMENT) 0

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl

if { [file exists $filename] == 1} {

source $filename

}

I would remove glb_* and pl_resizer_* config, run. Then you have to debug it using report timing and openroad -gui

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does combinatorial logic always use less chip area than an equivalent lookup table?

Hi all, I have a question regarding caravel soc if anyone have idea about it. I have seen a digital pll block in caravel repo, is it actually an all digital pll that caravel is using or it's just a behavioral model of the actual analog pll?

Hello All, I have designed a decoder digitally with openlane flow and got gds files .The gds is having metal1 layer horizontal and metal 2 vertical and so on..I have few questions on that: 1. Is there nay specific reason ,the digital design(openlane flow is taking metal1 horizontally? 2. Is it possible to do some change in any file so that we can get metal1 vertically and Metal2 horizontally?

Hi all, Recently we are trying to utilize the riscv-dv utility provided by google to obtain a randomized assembly sequence for testing purposes of our design Can anyone provide some insight to this specific issue on setting riscv-dv on their setup? https://github.com/google/riscv-dv/issues/905 (Similar issues are also seen but no clear solutions are found as of yet) Thanks!

Hello, When I load the user_project_wrapper.def there are supply grids for vccd1, vccd2, vdda1 and vdda2. But we are only going to use vccd1. Can someone tell me if I can delete (or not load) the routes in metal4 and metal5 corresponding to the supply nets I will not use? I wonder if doing so could produce problems with the precheck.

can anyone recommend an Xilinx FPGA Board for learning RTL Design? I want to have a board, that i wont outgrow so fast. The only FPGA Board that I have access at work is a Spartan 3 Board, which is slightly out of date and I want to have something newer... I am thinking about the Cora Z7 or the AXU2CGA or B...

@Enno the Digilent Arty boards with Xilinx Artix 7 FPGAs seem to be great - works for me 🙂

I am more thinking about an Board, that is based around a Zynq...

abd un thinking, wheter the AXU2CG Series Boards are worth the extra money, since it has more cores, more Ram, more Logic Cells, etc. ... It would probably last me a longer time of my careers but its more than double the price of a digilent Cora Z7...

*and I am

Excuse me, could anyone indicate me where can I find the switching frequency of this technology?

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