Matt Venn
01/07/2021, 3:29 PMColin Marquardt
01/07/2021, 3:34 PMJecel Assumpção Jr
01/07/2021, 3:43 PMJecel Assumpção Jr
01/07/2021, 3:45 PMMatt Venn
01/07/2021, 4:00 PMArunAshok
02/12/2021, 1:09 PMMD ZAKIR HUSSAIN
05/30/2021, 7:08 PMPhilipp Gühring
05/30/2021, 7:45 PMmehdi
07/16/2021, 1:04 PMTommy Thorn
11/01/2021, 7:04 PMHarry Snell
11/03/2021, 8:11 PMTed
12/04/2021, 5:08 PMKennedy Caisley
01/21/2022, 12:43 AMnewbie
03/21/2022, 6:16 PMAnıl Berk
07/12/2022, 7:34 PM[ERROR]: There are setup violations in the design at the typical corner. Please refer to 'designs/mydesigns/VLSI-Workshop/Adders/runs/RUN_2022.07.12_19.28.51/reports/signoff/28-rcx_sta.max.rpt'.
My config.tcl :
# User config
set ::env(DESIGN_NAME) ripple_carry
# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/ripple_carry.v]
# Fill this
set ::env(CLOCK_PERIOD) "10.0"
set ::env(CLOCK_PORT) ""
set ::env(PL_TARGET_DENSITY) 0.7
set ::env(CELL_PAD) 2
set ::env(DIE_AREA) "0 0 400 400"
set ::env(FP_SIZING) absolute
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) 100
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
set ::env(FP_CORE_UTIL) 30
set ::env(PL_BASIC_PLACEMENT) 0
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
Arman Avetisyan
07/13/2022, 4:57 AMDiwakar
07/16/2022, 6:47 AMAndrew Hodges
07/31/2022, 10:04 AMSajjad Ahmed
08/06/2022, 6:27 AMDeepak
08/18/2022, 12:33 PMKe-Haur Taur
11/06/2022, 8:09 PMAlfonso Cortés
11/24/2022, 4:00 PMEnno
12/25/2022, 7:30 PMJulian Kemmerer
12/26/2022, 2:52 PMEnno
12/26/2022, 4:02 PMEnno
12/26/2022, 4:05 PMEnno
12/26/2022, 4:06 PMNelson Rodriguez
01/27/2023, 10:34 PMTim 'mithro' Ansell
03/31/2023, 5:31 PMAndrew Hodges
04/21/2023, 11:51 AM