@User if you are working on a ROM compiler, are you going to do this within openram? It is fairly straight forward to extend and then you would get all the views and models too

No, I'm targeting smallish ROMs and they'll be integrated in the standard cells along the rest of the logic (just a python script setting position and

FIXED

and routing it before the main placement/routing).

Why not synthesize the rom then?

(1) it should end up smaller (and hopefully faster too) and (2) I can update the content without re-running the flow.

I did some studies a long time ago for regular standard cell structures (in this case data paths) and concluded that the fixed placement actually reduced flexibility and produced worse results. Given that the logic in this case can also be reduced by logic synthesis, it would be interesting to compare.

Yeah speed is TBD ... For Space, I did a bit of testing for area and with a fairly regular rom content, the gain isn't huge, maybe only 30% smaller (because synthesis managed to optimize quite a bit), but it still have like 17 gate logic depth. Also this was with the OSS tools which barely manage a 50% density. While using hand placement here I have 95+% density. With random ROM content, the gain was way more substantial. Then of course all that synth opt would prevent any hope of updating the ROM content without re-running the flow. And given how difficult it was in the first shuttle to get a GDS out, the ability to change microcode rom, boot rom, character rom, etc ... without going through all that again (in what we submitted I needed quite a few manual edits after the run, so that's like 3-4 hours of manual work at each rebuilt, everytime with the potential of screwing up).