Hi, all, Is there any memory compiler for skywater130? From https://vlsida.github.io/OpenRAM/, it looks openram does not support skywater130. Thanks

No there isn't one public ATM. OpenRAM support for sky130 is yet to be published. There are some pre-made SRAM cores available, but they are yet to be silicon proven.

It looks this is a candidate https://github.com/shalan/DFFRAM Do you know other alternatives?

Ah yeah DFFRAM, but as the name implies, it's using DFFs.

Hey there, do you know where to find the pre-compiled models? I'm just looking for something I can use for testing design planning

thank you, I think this will work 🙂

Isn't .lib generated by OpenRAM? Then why isn't .lib info based on real values?

Because for OpenRAM to generate a .lib worth anything the analytical model needs to be done/caracterized ... and atm, it's not.

I was able to use it on dc/icc, besides expected charz issues, there were some mismatches between logic / physical. ie: extra wmask1 on .lib and wrong voltage used on model operating condition for some models

Did you manage to simulate it in spice or something ?

No, I'm only setting up SoC implementation flow for Synopsys. I meant to say that besides the dummy timing numbers, there are other model mismatches that I had to work around to consume the files.