https://open-source-silicon.dev logo
#sky130
Title
# sky130
p

Preet Batavia

07/22/2021, 1:04 PM
I am actually trying to design a basic mux with Openlane and this is the error i am facing in step 7 of the openlane design flow , if you could help me out with it.
h

Hieu Bui

07/22/2021, 1:57 PM
The error says "Utilization exceeds 100%". This means that you need to increase your floor plan area by increase the two last values in ::env(DIE_AREA) in config.tcl. You can also use the relative floorplan:
Copy code
set ::env(FP_SIZING) relative                                                                                                                                 
set ::env(FP_CORE_UTIL) 20
p

Preet Batavia

07/22/2021, 2:41 PM
Thank you so much , that rectified that paticular area , im getting another error in CTS , can I also put forth that to you /
This is the error im facing in detailed placement .
h

Hieu Bui

07/22/2021, 2:48 PM
I think maybe you can enlarge your design more. There are some overlaps that cannot be resolved.
p

Preet Batavia

07/22/2021, 3:20 PM
can u send me the part of config.tcl specifying ::env(DIE_AREA)
it isnt specified in the config.tcl that was made by the openlane flow in my case
and what do you exactly mean by enlarging the design ? , really sorry if i am bothering you , but im still a novice at this.
h

Hieu Bui

07/22/2021, 3:35 PM
You can find out all the configuration of Openlane here: https://github.com/efabless/OpenLane/tree/master/configuration. If you do not set them, they will get the default value. In your case, maybe you can try to comment out "set ::env(DIE_AREA)" and change FP_SIZING to relative and add FP_CORE_UTIL as follows:
Copy code
set ::env(FP_SIZING) relative                                                                                                                                 
set ::env(FP_CORE_UTIL) 20
p

Preet Batavia

07/22/2021, 3:52 PM
thank you so much
Hey, I have completed the design flow of a MUX successfully in openlane , i have various magic , spice files etc , i am not able to figure out how do i simulate it and visualize the inputs and outputs , please if you could help me out here.
h

Hieu Bui

07/23/2021, 11:23 AM
Which problem do you have? You can compile the gate-level netlist, the library and the testbench as you compile the RTL. Then you can simulate it and dump the vcd file.
p

Preet Batavia

07/23/2021, 12:58 PM
how do i compile the gate level netlist??
h

Hieu Bui

07/23/2021, 2:27 PM
It is similar to compiling the verilog RTL, you replace your verilog RTL with the verilog gate-level netlist and the library.
p

Preet Batavia

07/23/2021, 3:06 PM
oh ohk , but particularly do you have an idea on how to simulate it on ngspice. ?? , basically openlane has created a .spice file for me , im just not able to use it in ngspice
h

Hieu Bui

07/24/2021, 12:59 AM
Simulation using spice netlist will take a lot of time. But you can do it. If your design is purely digital it is not recommended. You will need to create a testbench for spice netlist and include the spice library for it.