Hi all, I was working with a PMOS which I generate...
# sky130
Hi all, I was working with a PMOS which I generated in Magic and I had this doubt. It's a single PMOS of width 3u x 42 and the body of this PMOS is connected to the VDD net. When I do a parasitics extraction, the spice file I'm getting indicates capacitive interaction with a 'VSUBS' net (image attached). Is it the P-substrate that this net is indicating? I tried linking P-substrate to the GND net but that did not change this observation after parasitics extraction. Could anyone let me know what this net stands for and why it comes up? I observe that this does not happen in case of NMOS.
Yes, VSUBS is the name that magic gives to the substrate node if it is not labeled something else. In your typical nMOS layout, the bulk of the transistor is connected to the substrate, and this should be tied to ground and is probably labeled with something that overrides the default name. In your typical pMOS layout, the transistor bulk connection is the nwell, but if there is not a larger circuit around the device, then probably your substrate is not connected to anything, so it gets the default name. This behavior will go away if, for example, you add a substrate contact below your pMOS device and label it, say, VSS.
That worked! Thanks.