Hey all , I am working on a research project using...
# sky130p
Preet Batavia
07/21/2021, 2:05 PMHey all , I am working on a research project using OpenLane , I am trying to load my own design verilog file but am getting the error as shown in the image. Please if someone could help me here.
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Dinesh A
07/21/2021, 4:13 PMTool is saying it's not finding top-model name with test
You may need set DESIGN Name correctly in config.tcl
set ::env(DESIGN_NAME) <Module Name>
<Module Name> should be top module name or in your case module name in design.v
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Preet Batavia
07/22/2021, 11:24 AMThank you so much for the support
Preet Batavia
07/22/2021, 11:24 AMI figured out the issue
Preet Batavia
07/22/2021, 11:26 AMI am actually trying to design a basic mux and this is the error i am facing in step 7 of the openlane design flow , if you could help me out with it.
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Dinesh A
07/22/2021, 2:37 PMTool is saying utilization is more than 100% .. "util%:116.67"
you need to increase you die size ==> set ::env(DIE_AREA)
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Preet Batavia
07/22/2021, 4:42 PMSorry , I'll try and let you know If I enter into any other issue
Preet Batavia
07/23/2021, 3:04 PMHey do you have an idea on how to simulate the spice file generated by openlane using ngspice