Hi everyone, i have a concern. If anyone wanted to design a processor then we all know it has adder, decoder, encoder etc etc. So, if i make an adder for my design, a flip flop then how all these files merged up to a one code which will execute in the form of a processor. And one more question, how can i set clock timings and knew about the whole path. Thanks!
01/24/2022, 2:14 PM
wow that's a broad question! Have you got HDL experience? If you design your processor in Verilog for example, then we can put the complete design into OpenLane and the idea is that we get a GDS file at the end to submit to Efabless. The clock speed you can set in the config.tcl file. You will get reports from OpenLane about how well you met your constraints.