I haven't tried it, as I'm dealing with analog only projects, but you could try VerilogAMS with Ngspice. It has some native support for mixed signal circuits with Xspice. http://ngspice.sourceforge.net/adms.html http://ngspice.sourceforge.net/xspice.html

I'm not sure what there is that can do this particular mixture. Using ngspice with Verilog-AMS is a pain because the models have to be compiled into ngspice. Xyce can compile a single shared object library for a device model and use it as a plug-in, which is much more convenient. For either one, though, I don't know whether they will compile Verilog-A, which is I think fully a subset of Verilog-AMS but I'm not entirely sure if it's 100% compatible. Then, the SystemVerilog has its own issues. To my knowledge, there are no open source tools that fully understand SystemVerilog syntax, although all the tools understand some subset of it. The best approach I've found is to first synthesize all of the verilog and generate a simple verilog gate-level netlist. Then, convert that netlist to xspice format. There is, in https://github.com/RTimothyEdwards/qflow , a script

spi2xspice.py

that will convert a verilog netlist to a SPICE netlist in xspice format.

I think I have seen an application note for Xyce that explains the co-simulation with Icarus. Haven't tried it myself. I don't think Icarus can simulate System-Verilog though.

Thanks all for your replies. Since the analog parts are DFFs, DAC, and MUX, is it better to write everything in Verilog? Is it meaningful if write all in SystemVerilog then use sv2v converter?

Xyce is the one that I know of that will be able (I think) to compile your verilog AMS model. But I think gnucap can do that, too. I'm not familiar enough with WRspice or Qucs to know if they can or not.