Is it possible to integrate the memory array generated using OpenRAM to the user wrapper?

Yes. 1. Build pdk with sram cells (they are prebuilt) 2. set EXTRA GDS and EXTRA LEF to sram cells 3. You need to configure the pdn to be connected to srams power pins 4. Integrate in your verilog 5. Run synthesis. It will generate netlist 6. Use names from netlist and place sram cells using macro.cfg 7. run the flow