I came across this (very old) paper https://ieeexplore.ieee.org/document/1050943 "High Density CMOS ROM Arrays" which, although very much out of date, gives a design of a CMOS ROM which seems reasonable to me. The thing I like the most is it uses dummy bit lines to determine the length of the precharge cycle, and is essentially asynchronous, i.e. a precharge cycle is initiated when an address line changes. I wonder if any one could tell me if there are newer design methods that are more suited to modern processes? I have access to journal papers and e-books through my work, although my searches only turned up this paper. Can anyone recommend any other resources (i.e. text books, papers?)
Interesting, the simple 8Kx16 ROM in xschem examples uses a reference bitline as well. using dummy elements is a good and very often used approach to calibrate sense amplifier timings. The ref bitline has all transistors connected so it is a kind of 'worst case' . When sufficient signal has been developed on this bitline the read can be done on all other bitlines.
10/08/2020, 8:27 PM
@Stefan Schippers Yes I was impressed by the 8k ROM example, but I couldn't get it to simulate for some reason, and understanding the many schematics was a little difficult for me without any frame of reference. If noone can suggest more modern references, I'll just work over that paper and implement a small ROM. Perhaps then I can understand your 8k design 🙂
@Ronan BARZIC yes that is a good question. I would like develop some automated script that can act as a silicon ROM compiler. Using OpenRAM as a starting point is a good idea, I'll have a look at it.
10/08/2020, 9:29 PM
@jrsharp Thank you for commenting the sample rom8k issues. I have committed some additional comments in the sample circuit.
To simulate the rom8k you need to copy one file (provided in the install directories ) into the simulation directory (where spice reads netlist and writes results) and follow the instructions, then download a model file. Just do a 'q' (edit attributes) on the 'STIMULI' code block and read.
Unfortunately i can not package model files with xschem as they are generally non free or without a license. I agree, it's not a trivial example (14K transistors, more than 6000 in circuitry, rest in (partially programmed) array) so some steps are needed.
@jrsharp when first trying rom8k i was not even convinced ngspice to be able to manage it. Not only it did, it completed the sim in a very short time
10/08/2020, 10:08 PM
@Stefan Schippers thanks for the tips. I'll look into simulating the design.
10/09/2020, 2:21 AM
@Ronan BARZIC: ROM is planned for the OpenRAM project. There is an #openram channel here if you want to check out what's going on with OpenRAM development for Sky130.