I'm still struggling trying to make a simple bandg...
# analog-design
I'm still struggling trying to make a simple bandgap. I just ran into an interesting find. My simulation results for sky130_fd_pr__pfet_01v8_lvt with l=1 w=5 m=2 are different from the same model with l=1 w=10. Shouldn't they be the same???
Whats that a plot of? drain voltage vs something? Or is this your bandgap output?
I believe that the models are based on collected data from test structures, and might represent some variation in nominal and width as fabricated, where the true sizing of the w = 10 and w=5 m=2 fets do not match
based on the texts I have been reading, if you need different widths you chose one width and just change the number of fingers, that gives better matching between FETs
also, I think the 1V8 fets models are only valid for voltages up to 1.8V. I see the X axis goes up to 5V so you might be running into issues with those models.
@Weston Braun Yeah this is the bandgap output. Not very good I know, but seeing things like this happen makes me think I can never get it anywhere near good. To get good matching you need more than just fingers, the devices need to be split into a centroid layout and maybe with opposing current flow AFAIK. But that may be old info, I don't know about newer processes. Anyway, I'm nowhere near the point where I worry about layout, I just want a fricking simulation to work well and I can't even get to that point so...
it should be possible. My best guess is its just due to the difference between nominal and actual transistor sizes between the two bins impacting matching
do you have your work online anywhere? I am interested in what others are doing (and I need a bandgap reference....)