@User: What do you mean by "support"? You mean what is already on the test harness? Essentially nothing. We got no analog IP from SkyWater, so we will have to create it all from scratch. I created a simple power-on-reset circuit for caravel for the first tape-out, and that's all on the management SoC side of the chip. There are a number of analog IP blocks among the 40 user submissions for the first tape-out, including (I haven't counted them) one or more bandgaps, ADCs, LVDS drivers, op-amps, PLLs, and LDOs. Once we are able to get results from the users testing their chips, I will be adding them to the harness in support of the management SoC (e.g., 1.8V LDO for driving the digital cores, PLL for the clock, LVDS driver option for high-speed I/Os).

yeah sorry i should have asked like what all analog ips do caravel test harness need

I have not given much thought to making specs for the essential analog IP blocks needed. I am waiting to get the first test chip back from packaging and assembly (should be in a couple of weeks) to get a measured range of the clock for figuring out what the spec should be for a pierce oscillator and a PLL (I do not know of any crystal oscillator designs on mpw-one, and we really need one. Or several). It would be nice to have a simple SAR ADC at maybe 10 bits, and a sigma-delta ADC at maybe 16 bits. Would be nice to have a set of high-speed drivers covering not just LVDS but also LVPECL and HCSL. Some R-C oscillators would be nice, too, especially if they are temperature-stabilized.

ok sir,now i got some idea

@Tim Edwards For the spice simulations of the blocks already in Harness, was Xschem used or anything else ? coud you explan the flow

@ArunAshok: Lacking anything at the time I did the design, my "flow" was to sketch out the circuit in my notebook with a pencil, and then create the layout by hand in magic. Verification was done by simulation, not by LVS. At some point (soon) I will create schematics for it, particularly as I want to demonstrate how to properly create and organize an analog design flow.

ah ok. How was the netlist for the simulation generated if not from schematic.