@User xschem is quite flexible for netlist generation. When you create a new component you define how the component gets netlisted in the spice netlist. One example is the standard

devices/bsource.sym

component where you can specify an arbitrary equation for voltage or current. Another example is the

devices/switch_ngspice.sym

that models an ideal switch. VerilogA primitives could easily be created and placed in a schematic and should link to some compiled verilogA code. I have not done specific tests on ngspice, i did that in the past on Hspice.

@Stefan Schippers this is very helpful. Thank you for the clarification on how that works!