p
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t
It would be nice to have both high speed and high voltage IP on Caravel. For the 2nd tapeout I want to make available a portion of the padframe swappable, so you can ditch the GPIO pads for straight-through analog pads and build the drivers and receivers yourself with high voltage capability and/or differential signalling.
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w
@Tim Edwards anything I can do to help with this / when will this be decided by? Two of the SKY130 projects at Stanford (high speed PHY and buck converter) need I/O access and are trying to talk to people at efabless to try to allow changes to the caravel test harness.
t
Who are they trying to talk to? I haven't heard anything about it. I can tell you some details because we just worked them out in a meeting that just ended. There will be a separate project wrapper for analog, and the top row of pads (9 pads total, because two are global power supplies) will be available as straight-through pins for whatever purpose the end user wants. The rest of the GPIO will still be available for digital or for analog low speed and voltage. Diodes and clamps will be available but unconnected. The user will be reponsible for ESD protection.
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w
I am not sure. The tapout plan for the class is pretty unclear but they have repeatedly told us we are going to be taping out and that we should expect to use the caraval test harness.
I have not looked at the caraval test harness closely, but what you are describing sounds like it would work. When do you expect the new wrapper to be available?
I have lecture for his class in a few hours, I will bring this up and report back.
t
Thanks, please do. The new wrapper should be done in a week or two, but you probably get the general gist of it. The wrapper will look the same except that there will only be the pad connections on top, and probably the diode end connections as well. The rest of the GPIO pads will bring the "esd" (direct-to-pad through 150 ohms) and "noesd" (direct-to-pad) connections into the wrapper as ports, for all the GPIO pins except for the ones that have dual use with critical management processor functions such as the SPI.
w
As long as its possible to route a large metal interconnect to it that sounds like it should work.
@Priyanka Raina is the professor for the class and has been workin on the tapeout logistics
p
I have been talking to Mohamed Kassem. He is aware of our analog projects, and mentioned that there may be caravel changes.
t
@Priyanka Raina: Feel free to contact me directly with any questions, as I am the designer and architect of the Caravel chip.