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#analog-design
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# analog-design
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Tim Edwards

04/06/2021, 2:05 AM
@User: I can't speak for the reason of it, but rule POLY.1b specifically restricts LVT pMOS gate length to >= 0.35um. The 0.30um bin is limited to a dummy device (for matching) found in some of the RF cell layouts, and is not allowed for an active device.
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Daniel Stanley

04/06/2021, 3:30 AM
Ok, thank you for the info