There is definitely quite a bit of weirdness in the nfet_01v8 and pfet_01v8 device models. If you fix the width of the nfet and plot gate characteristics on a log current scale, the weak-inversion regions wind up on top of each other. The output resistance in the saturation region scales with length in a very strange way, too. For the pfet devices, there are some unexpected humps and kinks in the weak- and moderate- inversion regions. What it would be really nice to see some actual measured characteristics…