There is definitely quite a bit of weirdness in th...
# analog-design
There is definitely quite a bit of weirdness in the nfet_01v8 and pfet_01v8 device models. If you fix the width of the nfet and plot gate characteristics on a log current scale, the weak-inversion regions wind up on top of each other. The output resistance in the saturation region scales with length in a very strange way, too. For the pfet devices, there are some unexpected humps and kinks in the weak- and moderate- inversion regions. What it would be really nice to see some actual measured characteristics…
The EKV model is too compact. Maybe the problem is that k is not constant. Anyway, it is very strange that the PMOS curves don't fit well for currents lower than 1 nA. The BSIM model parameters must be wrong for this region.
Even if you use the pinch-off voltage model in EKV v2.6, you don't do very well with the pmos devices. It would probably require some kind of nonuniform substrate doping profile as a function of depth into the substrate.