Nikhil Poole

05/24/2021, 9:00 AM
I'm running into an issue with netgen that I've now stared at for several hours. I have a layout and a schematic which match cleanly in terms of nets and devices, but for which netgen yields property errors for one of the devices. In particular, both my layout netlist and schematic netlist have exactly 3 dummy devices with all four terminals tied to VDD (can ctrl-F to verify), two of width 8um and one of width 6um. Netgen complains about a property error for one of these devices. However, when I explicitly change my schematic netlist such that all three devices are of width 8um, netgen yields no property errors and a perfectly clean result, despite the fact that one of the layout dummy devices has width 6um. How is this possible? I've attached both SPICE files and the comp.out file in the comments. Changing M55 in the schematic netlist to have a width of 8um instead of 6um yields no property errors despite the clear netlist difference.

Tim Edwards

05/24/2021, 12:38 PM
I hate mysteries. . . . I'll take a look at it. All this has to do with sorting properties, which is immensely complicated. This case seems really straightforward, though, which is surprising.
My suspicion is that in modifying the sorting algorithm to take care of capacitor matching, I somehow screwed up transistor matching.
Oddly, it was a bad assumption that has been in the code for a long time. Anyway, I just fixed it.

Nikhil Poole

05/24/2021, 6:55 PM