I have a very vexing LVS issue I can not resolve d...
# analog-design
I have a very vexing LVS issue I can not resolve despite a lot of manual checking. is it possible that a submodule that passes LVS itself can cause LVS to fail once included? I know that LVS will not catch things like you flipping the + and - pins of an opamp.
Yes, it should catch things like flipping the + and - pins of an opamp.
I can flip the input pins of opamps and netgen does not seem to catch it. Is there some flag to have it verify sub circuit pin order or something?
Huh, I have it narrowed down. My submodule passes LVS by itself, but when I compare the submodule in the extracted netlist of the larger design with the schematic netlist of the submodule it fails LVS
does magic cache mag files or something?
If you swapped input pins of an op-amp, then it would be viewed as a pin match failure. It might not be caught if the op-amp is the topmost level circuit you are checking for LVS, but it will show up if the op-amp is a subcell of the circuit you are checking for LVS. If not, then something is wrong with netgen.
Ok, this is weird.
my comparator passes LVS when flattened and not when un-flattened
When verifying the base module I reused a script that flattens it
and I was not flattening the higher level module.
is this something that should ever happen?
Is the circuit losing pins (pins converted to regular text) when flattening?
Top level ports, or just pins?
The number of top level ports looks the same
I don't understand what's going on, then. . .
I ran netgen on the two extracted netlists (flat and hirarchial) and they do not match
the only thing that is sorta weird is that my project partner routed this one and she drew some fets abutting the ones that are submodules
I dont know if that has anything to do with it? the drawn ones use the diffusion / drain contact of the submodule fets
Possibly. I need to look at the actual layout. There may need to be redundant diffusion in the same cell as the FET gate so that the extractor can see that it has both a source and drain independently of any subcell.
I guess the best approach now would be just to flatten the whole design and use that?
the design is DRC clean