What I'm desiring is the maintainance of a decent amount of Vgs-Vt overdrive in cascode loads. What I like to do is to have a fairly stiff pmos at the supply rail, but to have a cascode device that's more in moderate inversion. That smaller pmos would have a gate length a bit larger than the lithographic minimum, but I want to keep that pmos small to reduce the device capacitance that the signal path is exposed to. Of course the low Vt devices give me more headroom for cascoding. So - if the implant details are causing the larger L, then I have to live with it and go to a standard Vt device. However, if Skywater increased this min-L due to channel leakage only, than maybe I can still use it. @User how would I ask someone there why this minL exists?

I think that @Boris Murmann is right. The process is optimized for standard VT devices after all. All other non standard devices have larger Lmin. If you really want lower VT with standard devices, you can use forward-body-biasing or high swing cascode transistor configurations, such as the self-cascode. Forward-body-biasing for typical supply voltages. It also can be used for analog circuits. https://www.researchgate.net/publication/2977948_Dynamic_threshold_pass-transistor_logic_for_improved_delay_at_lower_power_supply_voltages Self-cascode, also known as composite transistors trapezoidal transistor arrays. It can be an alternative for cascode transistor configurations. http://www.lci.ufsc.br/pdf/_00309905.pdf

Thanks - I've definitely used body-biasing before to lower the Vt. However, for processes much smaller than 130nm, you need all the tricks in the book when your Vdd is 0.8-0.9V. Also - body biasing requires creation of iso wells for those devices - that can eat up area. I don't foresee much problem with 1.8V Vcc, but it's nice to know the options. I just posted a query on the skywater channel. Sansen has much on the topic of body-biasing in his text "Analog Design Essentials" - a great book on design in the post square-law world.

What is your application? A larger L has it's benefits, as it also lowers VT. It's just not that good for high-speed, as RF circuits, or digital circuits, where gate density is more important. Basic analog circuits with minimum L are harder to route, have worse output resistance, and, if they are too small, it suffers a lot of mismatch.

It's for analog up to the 0.5-1GHz range. The upper part of the cascode would be the small transistor, to minimize the device capacitance. And an upper transistor in the cascode doesn't impact the mismatch nearly as much as the larger, "stiff" device The circuit is well thought out - I'm only wanting to understand the reason for this one process limitation on the 1.8V lvt pmos.

You will really need all the tricks to achieve those frequencies with this power supply! If they could accept a smaller Lmin for the reduced VDS, your job would be indeed easier.

Yep 🙂 Cascodes are essential for this, as well as minimizing some of the device capacitances. There are techniques: pole/zero cancellation is one.