Is there a formula anywhere in the PDK to calculat...

# analog-designm

Murat Eskiyerli

07/13/2021, 8:51 PMIs there a formula anywhere in the PDK to calculate AD, AS, PD, PS parameters for MOSFETs? I have seen someone using 0.29um to multiply it by each finger's gate width. I cannot find any reference to it in the PDK. More importantly, are there any parametric cells for schematic or layout instances for any tool flow?

t

Tim Edwards

07/13/2021, 8:58 PMIf you want an *estimate* of the values, look at the xschem libraries for sky130, which are using the recommended method.

m

Murat Eskiyerli

07/13/2021, 9:00 PMWhere would you find the formulas for that recommended method?

t

Tim Edwards

07/13/2021, 9:04 PMYou can ask in the **#xschem** channel. I'm not sure if that came from documentation or just from assumptions about the minimum amount of diffusion needed for source and drain.

m

Murat Eskiyerli

07/13/2021, 9:07 PMI found them. The same 0.29(um?) number popping up in them as well. I suspect it assumes the minimum width for source and diffusion widths. For the layouts, are there any parametric cells created? I know very little of Klayout and no Magic.

s

Stefan Schippers

07/13/2021, 9:08 PMGiven a total width '`W`' and number of fingers '`nf`' the formulas are for (drain):

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```
ad=int((nf+1)/2) * W/nf * 0.29
pd=2*int((nf+1)/2) * (W/nf + 0.29)
```

For source as and ps same formulas are used.
The 0.29 value is presumably the minimum gate to contact + contact + diffusion endcap over contact.m

Murat Eskiyerli

07/13/2021, 9:12 PMThey make sense. Still need to dig in to design rules to make sure.

s

Stefan Schippers

07/13/2021, 9:14 PMthe tricky int((nf+1)/2) is used to handle transistors with even/odd number of fingers.

Stefan Schippers

07/13/2021, 9:16 PMI was mistaken, since in transistors with even number of fingers the number of drain/source areas are different these are the formulas used in the mos symbols.

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```
ad=int((nf+1)/2) * W/nf * 0.29
pd=2*int((nf+1)/2) * (W/nf + 0.29)
as=int((nf+2)/2) * W/nf * 0.29
ps=2*int((nf+2)/2) * (W/nf + 0.29)
```

m

Murat Eskiyerli

07/16/2021, 7:43 PMSorry I was in a hurry when I answered the question. My answer was really about multiple devices, not multiple fingers.

Murat Eskiyerli

07/16/2021, 7:44 PMFor multiple fingers, if nf is even: AS= W x l AD= (nf-1) x (W/nf) x l

Murat Eskiyerli

07/16/2021, 7:44 PMif nf is odd, then AD=AS=W* l

Murat Eskiyerli

07/16/2021, 7:46 PMOf course, it is a gross simplification. First of all we need to know two design rules: minimum distance from contact to poly gate and minimum coverage of contact by diffusion. The figure below shows the idea in lambda rules:

Murat Eskiyerli

07/16/2021, 7:47 PMBecause design rules are just numbers without any plots, its difficult to get an idea about these spacing rules. I think the minimum contact size is 0.17um and spacing is 0.19um. Correct me if I am wrong.

Murat Eskiyerli

07/16/2021, 7:49 PMThus, the use of multiple fingers may not bring much advantage in reducing the junction parasitics in drain. Cadence parametric cells quite often has the option of

Murat Eskiyerli

07/16/2021, 7:50 PMswapping Source and Drain diffusions if for example you are more worried about reducing source capacitance, e.g. in common-gate amplifier.

Murat Eskiyerli

07/16/2021, 7:51 PMFor layout design rules, it would be very beneficial Skywater were to release drawings for the rules with various spacings.

t

Tim Edwards

07/21/2021, 1:30 PMThere are drawings posted with the design rules, although they are poorly done and sometimes hard to read. It's all that SkyWater has, though.

m

Murat Eskiyerli

07/21/2021, 2:07 PMThen they need to improve it if they want to be in the foundry business.

Murat Eskiyerli

07/22/2021, 12:59 PMI checked a gds for a gate from the library. I think the minimum diffusion width is 0.26um if there are poly at both sides and 0.255um if there is poly only on both sides for PMOS. I think the discrepancy should be a result of spacing rule between licon and poly. For NMOS, the rules seem to be 0.28um and 0.285um for NMOS.