I'm trying to simulate an extracted spice netlist ...
# analog-design
m
I'm trying to simulate an extracted spice netlist of about 50 cells. I'm trying for 5 clock cycles over 20ns. It's taking forever! Are there any techniques to speed up spice simulation of larger designs?
m
Xyce! You can also do things like increase the time step in the .tran statement. ngspice can also be told to run in parallel by adding this to a .spiceinit: set num_threads=4
m
can you recommend a Xyce tutorial?
m
This will only speed up the BSIM model evaluation if you have it compiled with OpenMP. So, the more devices the better. However, it doesn't speed up the matrix solve
No, I don't know of any
We have been pretty active in #xyce though
Although, 50 cells shouldn't take "forever" so it is likely a setting
m
well, my patience is limited. I'm only waiting 20 minutes till I kil it
it loads the libraries, prints the message about timescale and then sits there eating memory
m
Are you using an old version of ngspice? There were bugs that prevented library reading in early versions
m
ngspice-34
m
That should be fine
t
@Matt Venn: If you are simulating a digital standard cell circuit, then ngspice will get bogged down because its methods are much better suited to smooth signals and not the sharp edges of digital signaling. Xyce may do better. If you are doing a mixed-signal design, then the best method is to simulate the digital part using xspice, which is a digital event-driven simulator inside ngspice.
e
Where is it hanging? Did it find the DC operating point?
m
I was just trying a transient simulation. Hangs after printing 'timescale'
but I only left it 20 minutes.
@Tim Edwards problem with doing a digital simulation is that I'm wanting to explore this hardware trojan idea further. So I want to change a pfet to an nfet in a standard cell and check it breaks the operation in the expected way.
hence why I'm doing a full extraction rather than blackbox
t
One problem with that is that the trojan is creating things that are not recognizable to magic as devices. The changing of, say, the p+ implant to n+ implant does not turn the p-FET into an n-FET; it turns the p-FET into a varactor. (I've forgotten the details of the paper, which layers were modified.)
m
Yes so my plan is extract the cells then manually change the pfet/nfet in the spice file
I'll make the GDS mod with magic but I don't expect to extract that mod
j
@Matt Venn If you can solve the problem of speeding up SPICE, any SPICE, by 10x, call Cadence; they will buy your solution for $100 Million USD. In the meantime, keep your simulations down to about 100 or so transitions per run. Alternatively, you can do what experts do in semiconductor companies: design all digital using an HDL flow and a mixed signal simulator or run simulations for days, and sometimes a week or more, using the highest compute platforms available.
šŸ¤£ 1
m
Yep I'll let them know!
I'm trying to get a handle on what's a realistic size of circuit. So 40 odd cells takes more than 20 mins for 5 clocks
I'm expecting slow but wasn't expecting that slow
j
@Matt Venn It has been that way for decades. No one has come up with a fast way to invert a circuit node matrix. So companies play tricks like breaking a circuit apart and running the pieces in parallel. This is not as precise as SPICE, but in the hands of experts, they know when the results are wrong and revert to the ages old SPICE matrix solvers.
e
Try looking this over. Lots of important advice
Most especially, make sure you use ngspice-34
m
thanks Eric
e
Copy code
ngbehavior=hsa
in the spiceinit seems important.
I just simulated a design with 60 cells and thistran 10ps 4ns 0 20p UIC
Took ~15s on my machine
m
could you share it somewhere?
e
add.example.tgz