I m unable to get my 50 cell design to simulate in a reasona

Question

I m unable to get my 50 cell design to simulate in a reasonable time so have given up on that and vastly simplified the design Now I have a new problem where a vector is missing I just can t work it out could someone put me out of my misery and take a look What am I doing wrong

Matt Venn · Answer

Matt Venn · Answer

in gds run ngspice simulation spice and it will fail with a message about no vector called lock

Matt Venn · Answer

lock is the output of the design and is directly connected to a flip flop

Matt Venn · Answer

I think I ve worked out that if a node never changes then no vector will be created not sure about that

Matt Venn · Answer

but the verilog test bench that does the same thing clearly shows the output togggling

Tim Edwards · Answer

< Matt Venn> Your top spice file contains black box entries for all the standard cells which means your netlist is effectively empty of any devices This is probably the result of extracting the netlist from a layout using abstract views of all the standard cells

Matt Venn · Answer

thanks Tim

Matt Venn · Answer

I m still such a newb at the spice stuff

Matt Venn · Answer

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