open-source-silicon.dev

Also i noticed that the DRC rule for p-tap only kicks in the moment i try to add a substrate contact.
If i didn’t have one to begin with i no get DRC errors but once i add it i see a ton of DRC errors on p-tap for transistors that are relatively far away .
So is there some sort of global substrate bias im over ridding?

I know i can use a deep Nwell to isolate some of the nmos but my entire circuit has a fixed body bias.

I assume you meant to say that the rule is that n-diff to p-tap distance must be less than 15um, not 0.15um.

By default, the layout will have a single substrate bias of ground, if you have all nFET devices, or whatever the nwell is connected to if you have all pFET devices.  If you want a body bias on nFETs that is not ground, then you need to have all those nFETs in deep nwell.  In your case, it sounds like you want to drop a deep nwell structure under your entire circuit.

The DRC rule for tap distance is always present but only if you have the DRC style set to "drc(full)", since the tap spacing computation is compute-intensive, and is not something that you normally want running interactively.

<@U016EM8L91B> thank you for that clarification.