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AndrewSftD

07/20/2020, 11:19 PM
really a digital PLL already ? that works right ?
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Tim Edwards

07/21/2020, 12:19 AM
I designed the ADPLL (which is actually a frequency-locked loop, not a phase-locked loop), which is only verified in simulation. So "works right" can only be said provisionally. Also it has very high phase noise, because it is switching in and out delay stages in a ring oscillator. Not the best design, but I didn't have the time to design a proper PLL.
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AndrewSftD

07/21/2020, 12:23 AM
ooook, i guessed as much, I already saw a couple of days ago you are the person to talk to about clks
I will take some time to try all of this out
and maybe one day when you are not so busy we can have a chat
and you can pass on some advice
thank you by the way for everything, I know you where also a part of all this effort
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Tim Edwards

07/21/2020, 3:13 PM
Thank you, much appreciated!
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user

07/21/2020, 8:54 PM
Indeed excited here as well. I am going to try the klen source for the first time. @Tim Edwards: does the phase noise be simulated?.
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Tim Edwards

07/22/2020, 7:41 PM
@User: I will post the digital frequency-locked loop example on my website when the device models are in the Google/SkyWater repository (otherwise you can't simulate anything). Phase noise is pretty easy to determine because if it is an N-stage ring oscillator, in my subcircuits each stage is divided into three delay stages, and there is a 3-bit thermometer code trim for each stage. Whatever trim values result in periods that are just greater than and just less than the target period, the output clock will toggle between those two periods in a ratio that, on average, produces the correct clock frequency. The difference between those two clock periods determines the cycle-to-cycle phase noise.
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user

07/22/2020, 8:12 PM
@Tim Edwards thanks. I look forward for the pll design.
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user

07/22/2020, 8:58 PM
Meanwhile, what are the tools used for pll design. I mean for spectre models, the same tools could be employed is it not
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Tim Edwards

07/24/2020, 1:11 AM
I just used ngspice with the SPICE models (they're coming soon; I'm working on preparing them for the repository) and simulated over corners to make sure I was hitting the target range of frequencies over all the trim values. Then I simulated the locking behavior with a mixed-mode simulation using ngspice (with the built-in xspice event simulator).
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Andy

07/25/2020, 3:44 AM
Any rough ETA on when you'll add the spice models to the repo?
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ArunAshok

07/27/2020, 4:00 PM
Thats is great to know. Do you have any tutorial for that. I mean to get started with ngspice.
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Tim Edwards

07/27/2020, 6:51 PM
@ArunAshok: I intend to provide the example of the digital frequency-locked loop circuit I designed for the efabless striVe processor, which will show how to set up and run a SPICE testbench.
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ArunAshok

07/27/2020, 9:06 PM
Good to know. Waiting :)
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Tim Edwards

07/28/2020, 1:28 AM
@ArunAshok: Won't be today or tomorrow. Still getting device documentation up (now going through edits), and then the files (models and subcircuits need to be separated and placed in the right locations).
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ArunAshok

07/28/2020, 7:57 AM
Yes, I understand. An update in the channel would be great.