Hi @Matt Liberty @Mitch Bailey. I've found myself in a catch-22 situation with the ports. If I fill the entire port box with Metal 2 right to the edge, Openlane won't get past Step 10 - Global Routing - due to congestion. Even just one port filled this way causes a failure - as can be seen by the GUI image

image.png,image.png

If I leave a tiny gap unfilled at the bottom edge of all the ports, it gets past Step 10 no problem. However, it then fails the klayout_pin_label_purposes_overlapping_drawing_check during tapeout precheck, on all those 53 bottom pins.

Is the only option to harden my macro into user_project_wrapper GDS with a small gap, and then, before the tape-out precheck, edit user_project_wrapper GDS manually to fill in the gaps?

When I paired my project (neuron_core_32, I successfully ran openlane with wishbone bus interfaces) into user_project_wrapper (check for me to see if I did it correctly). When running, it gives the error: [ERROR GRT-0039] Found pin clk outside die area in instance mprj.

Hello, I don't understand OPENROAD Atenna Rule Check clearly. In my design I don't use atena. so I removed the atena related parameters in config.json. I got a break at this step with the error: [ERROR]: There are violations in the design at the typical corner. Please refer to '../home/nam/edabk_new_project/efabless/caravel_user_project/openlane/user_project_wrapper_ver_1/runs/23_11_02_04_42/reports/signoff/21-rcx_sta.min.rpt'. Please help me

Hello, my project does not violate anything, but when it is merged with the user project wrapper, the setup slack will be violated. Can anyone tell me where I'm having problems?

Hello All, I have a couple of ring oscillator cells that have a height of 8.8um that I am attempting to include in the openlane flow as individual cells that ultimately interface with a mux16x1 design synthesized and PNR'ed inside of the openlane flow using the

sky130_fd_sc_hd

standard cell library. I have successfully gotten through detail and global routing but I have hit a snag on the

PDN

settings as I get this error on

STEP 22

of the openlane flow:

[ERROR]: during executing openroad script /openlane/scripts/openroad/irdrop.tcl
[ERROR]: Log: ../import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/logs/signoff/22-irdrop.log
[ERROR]: Last 10 lines:
Reading design constraints file at '/import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/tmp/floorplan/3-initial_fp.sdc'���
[INFO]: Setting RC values...
[INFO PSM-0001] Reading voltage source file: /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/test.csv.
[INFO PSM-0002] Output voltage file is specified as: /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/reports/signoff/22-irdrop-vccd1.rpt.
[INFO PSM-0015] Reading location of VDD and VSS sources from /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/test.csv.
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[INFO PSM-0031] Number of PDN nodes on net vccd1 = 843.
[ERROR PSM-0042] Unable to connect macro/pad Instance ro1 to the power grid.
Error: irdrop.tcl, 35 PSM-0042
child process exited abnormally

[ERROR]: Creating issue reproducible...

Where ro1 is a ring-oscillator instance that I instantiated in the

rtl

directory. Here are some of my

config.json

settings found in the

user_project_wrapper

directory:

"DESIGN_IS_CORE": 1,
    "FP_PDN_CORE_RING": 1,
    "VDD_NETS": [
        "vccd1"
    ],
    "GND_NETS": [
        "vssd1"
    ],
    "FP_PDN_CORE_RING_VWIDTH": 3,
    "FP_PDN_CORE_RING_HWIDTH": 3,
    "FP_PDN_CORE_RING_VOFFSET": 14,
    "FP_PDN_CORE_RING_HOFFSET": 14,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "FP_PDN_VWIDTH": 3,
    "FP_PDN_HWIDTH": 3,
    "FP_PDN_VOFFSET": 0,
    "FP_PDN_HOFFSET": 0,
    "FP_PDN_VPITCH": 186,
    "FP_PDN_HPITCH": 186,

I have been trying to follow the document found here but I haven't had any luck. Anyone happen to know how to configure the PDN settings correctly for this scenario? Thanks in advance!

Hi, After several trials with different macro placement combinations, our eFPGA design can not pass DRT (detailed routing) stage. We waited hours, but after a dozens of iterations still no progess on violations. I added placement image and detailed.log files. Do you have any suggestion? Regards,

hello, I tried to view the test design output followed the documentation and get this error, I tried "sudo docker run..." instead of "make mount" but still not work, anyone have ideal to fix that?

Hi what can cause openlane to generate a wrong lib file, I have a module with 20-bit width ports such as: output [0:19] chanx_right_out; After I hardened this module and instantiated in the wrapper, openlane give error in Synthesis step complaining about: "ERROR: Incompatible array type 'chanx_left_in' : bit_width=18, bit_from=0, bit_to=19" When I check the lib file it is written there: lu_table_template(template_1) { variable_1 : total_output_net_capacitance; index_1 ("0.00050, 0.00126, 0.00319, 0.00806, 0.02037, 0.05146, 0.13002"); } type ("chanx_left_in") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_left_out") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_right_in") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_right_out") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } After I manually edit lib file by changing bit_width from 18 to 20 the flow passes I attached verilog, sdc and lib files for the related module

OpenLane question: Can I somehow provide port numbers in the OL/OL2 flow so that the terminals in the extracted SPICE netlist are not all mixed-up? @donn @Tim Edwards

Hopefully I’m wrong, but it looks like there might have been a change to openlane in April that causes magic drc errors to be ignored. I suggest checking your

drc.rpt

files. If you have a non-empty

drc.rpt

file and an empty

<http://drc.tr|drc.tr>

file, openlane probably did not flag the magic drc errors.

Hello 🙂 we have integrated another 2 user's designs in our user_project_wrapper, and some slew/cap/fanout violations have appeared. They appear to be associated with just one of the added Macros. Just wondering whether these will only affect that one design (or whether the whole chip and all of our designs on it will be affected?) Any idea if these numbers are acceptable? Any help appreciated!

image.png

image.png

Hey, does anyone have a link to a project that was able to specify their own standard cells without creating a custom pdk?

Is it possible to run the tools that live in the Openlane docker environment from the command line, so that they don't have to be installed separately? (Magic, Yosys, etc) Without running 'make mount' ?

@Ellen Wood Not in a manner that wouldn't be even less convenient: you'd basically have to copy the entire command

make mount

runs and then add the tool to the end, i.e.

docker run --rm -v /Users/donn:/Users/donn -v /Users/donn/efabless/openlane:/openlane -v /Users/donn/efabless/openlane/empty:/openlane/install -v /Users/donn/.volare:/Users/donn/.volare -e PDK_ROOT=/Users/donn/.volare -e PDK=sky130A  -ti efabless/openlane:1d46ea5fb2303b571e530c56d7d91a89d9c59b16-arm64v8 yosys

It's a hassle

Hi all, is there any example testbench, makefile, or documention/instructions, of how to do a gate level simulation of our digital design within the whole chip (including the Management SoC)? In Verilog (not cocotb)?

Hello, I am experiencing an issue with the flow. Kindly see attached images, the flow appears to be completed successfully. However, upon inspecting the files, such as the Synthesis Timing file (which includes both positive setup and hold times), and in the SignOff folder where the summary file indicates that both TNS and WNS are negative, I am confused. If the setup is negative, how can the flow be considered complete? Secondly, do we only need to consider typical corners? If setup and hold times meet in typical corners, can we ignore violations that occur in the SignOff folder? Or do we simply need to ensure that the flow is complete and green, indicating that the design is ready for fabrication?"

I know this is a late question, but how do we upload our projects on the new efabless shuttle system? I can push small files to the generated Github just fine, but when I try to push a large file (such as my 900 MB GDS file) I get what seems to be a server side error

remote: fatal: error when closing loose object file: Input/output error
error: remote unpack failed: unpack-objects abnormal exit
To <ssh://repositories.efabless.com/chompfish/REPONAMEHERE.git>
 ! [remote rejected] main -> main (unpacker error)
error: failed to push some refs to '<ssh://repositories.efabless.com/chompfish/REPONAMEHERE.git>'

Any help is appreciated.

Hello, I had a small issue with PDN generation. Fragments of vertical VDD grid were generated, but only slightly touching horizontal traces, with no chance to put via. VDD net is highlighted on the picture. VSS rails are correctly not generated here. This causes LVS issues at precheck script (and FP_PDN check fail, but I had it disabled by default script 😞 ). I solved this issue by moving the bottom macro a little bit up to block this space. Is this something worth reporting to openlane or a standard problem? And additional question - is there some simple way to define additional PDN blockages in free space (outside of macros) in wrapper?

One, hopefully, final question; I am getting a single metal density DRC error flagged at the end of the "Tapeout" job for the CI 2311 Efabless shuttle. I believe this to probably be erroneous considering that neither the precheck nor the openlane flow flagged a DRC error. Is it possible to get a staff override to submit the project anyway and risk it? The applicable files are klayout_met_density.log

li1_ca_density is 0.47395094282908934
m1_ca_density is 0.6091835028867986
m2_ca_density is 0.6503541638094675
m3_ca_density is 0.5675005865615865
m4_ca_density is 0.49608642403511616
m5_ca_density is 0.49797430080492255

and klayout_met_density_report.xml

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>Density Checks</description>
 <original-file/>
 <generator>drc: script='/opt/scripts/tech/met_density.lydrc'</generator>
 <top-cell>caravel_231187f2</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>m2.pd.1e</name>
   <description>0.65 max m2 ca pattern density</description>
   <categories>
   </categories>
  </category>
 </categories>
 <cells>
  <cell>
   <name>caravel_231187f2</name>
   <variant/>
   <references>
   </references>
  </cell>
 </cells>
 <items>
  <item>
   <tags/>
   <category>'m2.pd.1e'</category>
   <cell>caravel_231187f2</cell>
   <visited>false</visited>
   <multiplicity>1</multiplicity>
   <image/>
   <values>
    <value>polygon: (5.965,6;5.965,5194;3594.035,5194;3594.035,6)</value>
   </values>
  </item>
 </items>
</report-database>

Particularly it seems the max density is set to 0.65 and the recorded density is 0.65035 so I don't think it would cause any errors

How can I generate a pad frame around my design in order to perform full chip simulation?

I have a macro available. I want to incorporate that macro into my design. I created my design macro. Then combine that design macro into user_project_wrapper. So what do I need to do to complete my idea? I tried incorporating macros into my design but I don't know how to properly configure the config.json file. Can someone help me? Please

Hello, has anyone had any success running OL or OL2 on Rocky Linux or CentOS? 🙂

Hi all, I have hardened a processor, does anyone know if in any of the reports that are generated in the process is provided the maximum operating frequency of the circuit or otherwise anyone has any idea how you could estimate or calculate a maximum operating frequency from some other metric that is generated in any of the reports.

Hello. I tried to put macros into my project. I have finished placing the macros and setting up the config.json. I proceed to run openlane for synthesis and tapeout. I get a Running Global Routing error code. Specifically, the error: [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load /home/edabk/efabless/caravel_user_project/openlane/neuron_core_dffram/runs/23_11_28_11_46/tmp/routing/groute-congestion.rpt in the DRC viewer.