Hi Friends, Very beginner question coming. I have hardened a small design ( a 4 bit counter), and now I want to harden a small core containing 2 counters and some dummy circuitry. The whole objective is to harden a complete chip and document it. I am currently having a tough time trying to solve a PDN generation of the core. The counter macros were generated with the following config.tcl:

# User config
set ::env(DESIGN_NAME) counter

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "10.0"
set ::env(CLOCK_PORT) "clk"

#set ::env(FP_CORE_UTIL) 5
set ::env(PL_RANDOM_GLB_PLACEMENT) 1

set ::env(FP_SIZING) "absolute"
set ::env(DIE_AREA) "0 0 100 100"
set ::env(PL_TARGET_DENSITY) 0.2

set ::env(FP_PDN_AUTO_ADJUST) 0
set ::env(FP_PDN_VPITCH) 25.0
set ::env(FP_PDN_HPITCH) 25.0
set ::env(FP_PDN_VOFFSET) 5.0
set ::env(FP_PDN_HOFFSET) 5.0


set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

The core has the following config:

# User config
set ::env(DESIGN_NAME) core

# Change if needed
set script_dir [file dirname [file normalize [info script]]]

#Verilog and macro files
set ::env(VERILOG_FILES) "\
    $script_dir/src/core.v"
    
set ::env(VERILOG_FILES_BLACKBOX) "\
    $script_dir/src/counter.v"

set ::env(EXTRA_LEFS) "\   
    $script_dir/macros/counter.lef"

set ::env(EXTRA_GDS_FILES) "\   
    $script_dir/macros/counter.gds"

#Floor plan 
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 500 300"
#set ::env(FP_CORE_UTIL) 20
#set ::env(FP_PDN_VOFFSET) 0
#set ::env(FP_PDN_VPITCH) 30

set ::env(FP_PDN_AUTO_ADJUST) 1
set ::env(FP_PDN_VPITCH) 25.0
set ::env(FP_PDN_HPITCH) 25.0
set ::env(FP_PDN_VOFFSET) 5.0
set ::env(FP_PDN_HOFFSET) 5.0

set ::env(FP_PDN_CHECK_NODES) 0

# Cell & Macro Placement
#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.35


# Clock  
set ::env(CLOCK_PERIOD) "10.0"
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_TREE_SYNTH) 0


set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

I am getting this error: [ERROR]: PDN generation failed. [ERROR]: You may need to adjust your macro placements or PDN offsets/pitches to power all standard cell rails (or other PDN stripes) in your design. Does anyone has any idea how to solve it?

Just a guess, but you have the macro placement line commented out.

#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg

Does anyone know if openroad/openlane supports automated macro placement?

A picture is worth a thousand words. Please post an image of the floorplan you are having trouble in pdngen with

@Mitch Bailey If user give EXTRA_LEF/DEF/GDS and macro.cfg not defined tool will place the macros randomly.

also, I would just leave the pdn settings. they almost always work fine

Hi friends, Many thanks for your answers! I think I figured out how to create the core with and without additional logic on the top module (pictures attached). These examples may suffice to glue modules in analog mixed-signals chips. The solution came by reading the documentation, something I should have done from the very beginning 🙂 . I am sure many newcomers with or without experience will definitely face some initial trouble, so I decided to put these fundamental examples in github so others can use as reference examples: https://github.com/saul-rodriguez/OpenLane_reference_designs I will add explanation for these reference designs so that they can be used in teaching at undergraduate level. Please feel free to take a look and comment if things can be improved. One important thing is that the OpenLane documentation seems to be fragmented in 2 different parts: https://openlane.readthedocs.io/en/latest/ https://openlane-docs.readthedocs.io/en/rtd-develop/index.html