<@U012WPP54FR> (<@U0174MP1W6Q>) : I am working o...
# openlane
@User (@User) : I am working on monte carlo simulation which is the only thing I don't know how to do (yet) in ngspice (there are spectre-specific methods for monte carlo simulation that need to be converted). "qflow" has support for generating xspice models out of any standard cell set for which you have a liberty file, so the script "spi2xspice" in qflow can be used to turn any synthesized digital circuit into an xspice model which will then simulate as a digital switch-level circuit, much like running iverilog on a gate-level netlist. It simulates slower than behavior verilog but thousands of times faster than simulating a digital block on the transistor level. It also simulates concurrently with the analog simulation, so it is a true mixed-mode simulation.
In case is useful… I have a ngspice unit case that runs by updating UT0, VTH parameters on the OnSemi 0.5u transistors, I guess would be shareable if I remove the parameters and keep the wrappers. Are there specific parameters blocking you?
I uploaded anyway, may still be useful to someone https://github.com/20Mhz/spice_decks/tree/master/ocv_mc