tnt
07/28/2020, 12:44 PMposedge
FFs to negative edge ones ( sky130_fd_sc_hd__dfbbn_2
) prefixing the clock path with an inverter ... I'm not a big fan of that.20Mhz
07/28/2020, 12:46 PMOpenROAD-flow/flow/util/markDontUse.py
tnt
07/28/2020, 12:49 PMnegedge
in my verilog, I'm fine, it can use it.dfbbp
...20Mhz
07/28/2020, 12:56 PMtnt
07/28/2020, 1:02 PMAhmed Ghazy
07/28/2020, 1:04 PMno_synth.cells
file (incrementally allowing smaller and different cells, etc.). The file was created with the older set of tools. Cells, whose pins were difficult to access back then, were added to the list, so that's why many of the cells are of size 4. The file is at $PDK_ROOT/sky130A/libs.tech/openlane/sky130_fd_sc_XX/no_synth.cells
.tnt
07/28/2020, 1:07 PMno_synth
Tx ! I was grepping for dont
and use
and not finding it 😛