Mm yosys is converting some of my `posedge` FFs to negative

Question

Mm yosys is converting some of my `posedge` FFs to negative edge ones `sky130 fd sc hd dfbbn 2` prefixing the clock path with an inverter I m not a big fan of that

20Mhz · Answer

have you tried below `OpenROAD flow flow util markDontUse py`

tnt · Answer

Yeah I could mark those as don t use but it s not that I object to negedge FF I just don t like it inverting the clock to use them stuck out tongue But if I have a `negedge` in my verilog I m fine it can use it

tnt · Answer

What surpises me though is that I think there is a posedge version of that exact same FF in the std cell library

tnt · Answer

Yeah there is a `dfbbp`

20Mhz · Answer

I see your point doc mentions use of inverters is acceptable may need enhancement There is also an optional selection argument to dfflibmap you may be able to work around this if you can identify the problematic banks beforehand

tnt · Answer

Where is the don t use list in openpdk

Ahmed Ghazy · Answer

Feel free to revise experiment with the `no synth cells` file incrementally allowing smaller and different cells etc The file was created with the older set of tools Cells whose pins were difficult to access back then were added to the list so that s why many of the cells are of size 4 The file is at `$PDK ROOT sky130A libs tech openlane sky130 fd sc XX no synth cells`

tnt · Answer

Ah yeah `no synth` Tx I was grepping for `dont` and `use` and not finding it stuck out tongue