open-source-silicon.dev

<@U017E7L119N> would you mind sharing with us the statistics of your copperv design? The size of the design, how many cells, and what it is?

sure, its really nothing fancy just the exercise of a risc/rv32i core from a collegue, any one stop shop report for the statistics?

```=== copperv ===

   Number of wires:              11557
   Number of wire bits:          11746
   Number of public wires:        1184
   Number of public wire bits:    1373
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11673```


thats odd, I’m pretty sure this is Verilog

But there is some VHDL library used for ... something else I guess in `util/`

<@U017E7L119N> Can you tell me what the die area was?

oh thats the OVL,  probably should have been a submodule instead

replace.log
```[INFO] DBU = 1000
[INFO] SiteSize = (460, 2720)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (740600, 745280)
[INFO] NumInstances = 19283
[INFO] NumPlaceInstances = 11673
[INFO] NumFixedInstances = 7610
[INFO] NumDummyInstances = 0
[INFO] NumNets = 11746
[INFO] NumPins = 39650
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (746515, 757235)
[INFO] CoreAreaLxLy = (5520, 10880)
[INFO] CoreAreaUxUy = (740600, 745280)
[INFO] CoreArea = 539842752000
[INFO] NonPlaceInstsArea = 10872928000
[INFO] PlaceInstsArea = 153618582400
[INFO] Util(%) = 29.041084
[INFO] StdInstsArea = 153618582400
[INFO] MacroInstsArea = 0```

&gt; any one stop shop report for the statistics?
Not yet, unfortunately, nope.

<@U017E7L119N> Thank you!
Also you might be interesting in trying the run_designs.py script. It will produce an automatic report and it can try different configurations on the same or different designs at the same time