Hello, I encountered an error during synthesis which does not give much insight to the problem itself. Please let me know if anybody has any idea regarding it. The error is:

10.1.2. Re-integrating ABC results.

[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /openLANE_flow/designs/design_top/runs/first_run/logs/synthesis/yosys.log |& tee >&@stdout"

[ERROR]: Exit code: 1

[ERROR]: Last 10 lines:

child killed: kill signal

can you try different SYNTH_STRATEGY values? maybe run the -synth_explore option in flow.tcl? Otherwise, it may be a running out of RAM issue.

Ok i would try that. @Amr Gouhar What does -synth_explore do?

@Wajeh ul hasan: it tries synthesizing with the 4 different values for SYNTH_STRATEGY, and it produces a nice table with a graph that should be a good indication on which ones passed and with how many cells and which didn't. I see that it's missing from the documentation. I'll take care of that.

@Amr Gouhar This sounds nice. So, the results of this are saved in the

runs

directory as well?

@Wajeh ul hasan: Yes, under

runs/reports

as far as I recall.

@Amr Gouhar I updated the RAM as per your suggestion. This time the process terminated much earlier. So I

meld -ed

the two logs files to see the difference. The two log files are exactly the same until the later terminated with this error.

ERROR: TCL interpreter returned an error: can't read "scripts(22)": no such element in array

Here is the comparison of two files when they bombed.

@Wajeh ul hasan: I see that you have 2 million cells (and that's only an initial value) during synthesis. This is definitely a machine CPU/RAM issue. The biggest design I tried through the flow was 250k cells big. Do you have a memory inside your design that you could reduce?

Ok let me try that next

@Wajeh ul hasan: Mainly those two. However, you might want to check the

wns

reported by OpenPhySyn and increase the

CLOCK_PERIOD

accordingly. The higher the

wns

(in the negative direction), the more buffers OpenPhySyn will insert to meet the timing requirements given as

CLOCK_PERIOD

, the more congested the design will be.