Hi While running the flow on rc4 version I am getting an error during the global placement stage. Can anyone guide me how to resolve this?

can you try reducing FP_CORE_UTIL?

I had initially kept the FP_CORE_UTIL to be as follows:

set ::env(FP_CORE_UTIL) 20

I tried commenting ad rerunning it, and got this error now;

Usually, you need to reduce

PL_TARGET_DENSITY

when you reduce

FP_CORE_UTIL

.

Right. I tried reducing it and also tried running flow for a variety of FP_CORE_UTIL just to see a difference. I found out that the core area isn't sufficient. Is there a way to manually define CORE_AREA just like we can manually set DIE_AREA using

set ::env(FP_SIZING) absolute

set ::env(DIE_AREA) "20 30 2000 2000"

@Aireen Amir Jalal: There is no current method that I'm aware of, although DIE_AREA controls the CORE_AREA. Maybe @Ahmed Ghazy knows a way that I don't. As for the other message you're seeing, it's perfectly normal, the power grid is adjusting itself to fit properly within your small design, which shouldn't cause any issues. Also, is your design still crashing? If so, check this.

The above warnings are removed upon setting these variables:

set ::env(FP_PDN_VOFFSET) 4
set ::env(FP_PDN_VPITCH) 15
set ::env(FP_PDN_HOFFSET) 4
set ::env(FP_PDN_HPITCH) 15

However, the error in placement persists. I am not sure how to proceed further.

@Aireen Amir Jalal: How big is your design? Also, I'd prefer to see the warning rather than setting the values randomly, because if the values are inaccurate the power grid will be invalid which will in turn cause other issues.

@Amr Gouhar, I think I found the issue. My design contains three verilog files in the

src/

directory. The first picture below is attached for reference. What I am trying to do is run the design in such a manner that synth_ram (built-in design in openlane design directory) and CoreSCRVTop are included using the ``include` command in the memory_core.v file which is the top module. After that in the config.tcl file I just define memory_core.v file as the VERILOG_FILE variable as follows:

set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/memory_core.v

. Now when I prep design and run_synthesis no cells are being found hence no netlist gets created and the flow bombs at placement stage as it can't find any cells to place. picture 2 attached showing no cells being found. I ran the flow on synth_ram alone and there are cells present in the design and a netlist gets generated, but when I try to run it after including it to memory_core, the cells don't appear in the design. Is there a way to run multiple verilog files in a design?

There are multiple ways to do that, if you want to flatten the whole thing, then you can just set the following:

set ::env(VERILOG_FILES) $::env(OPENLANE_ROOT)/designs/aireen_test/src/*.v

Or group them by name:

set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/file1.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file2.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file3.v ]

This way you won't need the internal `include in each file. You can also harden the synth_ram and use it as a separate macro (check this as an example).

@Amr Gouhar, I tried hardening the synth_ram as a separate macro as flattening the design and `include both doesn't seem to work. No netlist gets created for them. Hardening the macro step made the flow run past the global_placement stage, but I got this message inthe detailed_placement step.

@Aireen Amir Jalal: Don't use `include in your files. If you want to harden the synth_ram and use it as a separate macro (check this as an example). Note the LEF, GDS, blackbox verilog, macro_placement.cfg. If you want to flatten the design, then don't use `include and do one of the following two methods: 1. You can just set the following:

set ::env(VERILOG_FILES) $::env(OPENLANE_ROOT)/designs/aireen_test/src/*.v

2. Group them by name:

set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/file1.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file2.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file3.v ]

This way you won't need the internal `include in each file.

Right. Thanks @Amr Gouhar, I'll try that.