Aireen Amir Jalal
11/09/2020, 5:42 AMAmr Gouhar
11/09/2020, 8:53 PMAireen Amir Jalal
11/10/2020, 4:58 AMset ::env(FP_CORE_UTIL) 20
I tried commenting ad rerunning it, and got this error now;Amr Gouhar
11/10/2020, 1:25 PMPL_TARGET_DENSITY
when you reduce FP_CORE_UTIL
.Aireen Amir Jalal
11/10/2020, 3:05 PMset ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "20 30 2000 2000"
Amr Gouhar
11/10/2020, 3:25 PMAireen Amir Jalal
11/10/2020, 4:05 PMset ::env(FP_PDN_VOFFSET) 4
set ::env(FP_PDN_VPITCH) 15
set ::env(FP_PDN_HOFFSET) 4
set ::env(FP_PDN_HPITCH) 15
However, the error in placement persists. I am not sure how to proceed further.Amr Gouhar
11/10/2020, 5:36 PMAireen Amir Jalal
11/11/2020, 3:56 PMsrc/
directory. The first picture below is attached for reference. What I am trying to do is run the design in such a manner that synth_ram (built-in design in openlane design directory) and CoreSCRVTop are included using the ``include` command in the memory_core.v file which is the top module. After that in the config.tcl file I just define memory_core.v file as the VERILOG_FILE variable as follows:
set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/memory_core.v
. Now when I prep design and run_synthesis no cells are being found hence no netlist gets created and the flow bombs at placement stage as it can't find any cells to place. picture 2 attached showing no cells being found.
I ran the flow on synth_ram alone and there are cells present in the design and a netlist gets generated, but when I try to run it after including it to memory_core, the cells don't appear in the design. Is there a way to run multiple verilog files in a design?Amr Gouhar
11/11/2020, 4:00 PMset ::env(VERILOG_FILES) $::env(OPENLANE_ROOT)/designs/aireen_test/src/*.v
Or group them by name:
set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/file1.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file2.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file3.v ]
This way you won't need the internal `include in each file.
You can also harden the synth_ram and use it as a separate macro (check this as an example).Aireen Amir Jalal
11/12/2020, 6:37 AMAmr Gouhar
11/12/2020, 5:37 PMset ::env(VERILOG_FILES) $::env(OPENLANE_ROOT)/designs/aireen_test/src/*.v
2. Group them by name:
set ::env(VERILOG_FILES) [glob $::env(OPENLANE_ROOT)/designs/aireen_test/src/file1.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file2.v $::env(OPENLANE_ROOT)/designs/aireen_test/src/file3.v ]
This way you won't need the internal `include in each file.Aireen Amir Jalal
11/12/2020, 6:40 PM