open-source-silicon.dev

What are fanout and node fanout count ?
They are unequal during lvs in openlane.
What can be done for this?

<@U01CZH7JG2G> Are you seeing errors inside the cells or at the module level?

Screenshot from 2021-01-06 14-38-11.png

Screenshot from 2021-01-06 14-38-26.png

<@U017X0NM2E7>  I was generating custom padframe and the errors are for corner pads pins.
Can you have a look at below images

I believe <@U016EM8L91B> said that he was still working on the extraction (spice side) for the IO cells.
Tim, any progress reports?

<@U01CZH7JG2G> (<@U017X0NM2E7>:  This LVS is done on a higher level, just looking at the pins on the I/O cells, not the contents of the I/O cells, so extraction is not the issue here.):  The second netlist, which I assume to be the schematic (?)  Reports that each of the corner pads has VCC_HIB isolated instead of connecting to the ring around the padframe.  These are shown in the LVS report as isolated nets like `_noconnect_52_` .  Note that VCC_HIB has no internal connections;  the openlane developers have added a fill cell to the supplementary set sky130_ef_io that is installed with open_pdks which connects the VCC_HIB bus to the neighboring VCCD.

<@U017X0NM2E7>:  Progress, yes, but there is some issue with substrate connectivity that was reported yesterday and may or may not be related to my failure to get an LVS clean extraction out of the I/O cells.  Other issues are caused by the SkyWater files, as for example they have two VDDIO rings on the power bus, and the netlists all have one VDDIO pin on every I/O pad cell, but these two rings are clearly not connected to each other inside any cell other than the VDDIO power pad.  These kind of annoyances are making my work difficult.