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If I use an internal clock divider to get a much l...
# openlane
m
If I use an internal clock divider to get a much lower clock frequency (like 100khz), I'd ideally like openlane to do CTS on that net. But if I set clk_net to my slow clock then the CTS fails with a message about not being able to find the net. Anyone done this?
j
Yes, I used both clocks provided by Caravel, though not one I generated as part of my design, but needing 2 clock trees. You can check my mpw-one project to see if there's a clue there? You will also need to provide an .SDC file whose content indicates the relationship between the two clocks for timing analysis and CTS. Don't forget to handle clock domain crossings in you design. 🙂
m
thanks Jean
could you link your project?
this is just for an internal clock divider so I think it doesn't count as 2 clock domains
so 10mhz enters, is divided by 256 to get around 50khz and then everything runs off that new clock
@tnt suggested that the slow clock should also get CTS, so that's what I'm lookig at
j
Also, why not use the second DLL provided by Caravel to generate the 50KHz clock?
m
Good point. I still need to look at the dll
btw @Jean, I looked into the dll and confirmed with @Tim Edwards, the DLL will only be able to generate clocks > 10MHz. This is because the output of the DLL ranges from 90MHz up and we have an 8x divider.
Tim suggested generating a clock from the picorv32 firmware
Or if low jitter is needed then use a clock divider
So I will be sticking with my clock divider but trying to get a CTS on it's output
t
@Matt Venn: Chalk that down as a feature to add to the next iteration of caravel: A secondary clock divider, or else just more bits to the existing dividers.
m
👍
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