Hi, I need to use latches in my design but the current openlane (yosys) seems does not map to the latch gate specified in the tech_map.v (with SYNTH_LATCH_MAP variable) and report errors when Executing Verilog backend (step 14)?
This design can successfully be synthesized with the old openlane version (rc:6) with the same configurations.
Does anyone know how to fix it? Thanks
seems it can pass the synthesis by flattening the design but got error if I set SYNTH_TOP_LEVEL=1?