HI, just a quick question - does "core level" refe...
# openlane
b
HI, just a quick question - does "core level" refer to the design top or user_project_wrapper i.e. should my config.tcl for the dut top have pdn related commands for core or for a macro ? I have no mind about whether I want to instantiate my design top as a macro in user_project_wrapper or as an rtl module, I am open to do either ways as specified. Thanks
m
your design can't be core, it has to be below metal 5 for the power routing to work
I would follow the user_proj_example flow
b
Sure, thanks
a
@Matt Venn I was trying to search for posts related to openlane's usage of set ::env(DESIGN_IS_CORE) 1 and it lead me to this thread. I am not following the comment about user macros needing to skip metal 5. This is unrelated to the OP's design, but say we have a design with macros containing metal 5 (I have that with MiM caps) -- can't we just obstruct that macro and still get the PDN to go around the obstruction layer? That's what we are hoping to do in the next couple days -- but it would be good to know if that will set off some failing flags, thanks!
m
I don't think so. with the current tools, the PDN is just a set of generated wires and you can only really control the pitch and offset. They won't route around any blockage
@Matt Liberty has added a new PDN to the latest openlane, which might be cleverer, but I don't know anything about it yet
m
pdn has always cut wires around blockages. If you aren't careful you can create a narrow channel that can't be powered but most of the time it works fine.
1
There is a lot more to what pdn does than just put wires on the pitch/offset grid but it is algorithmic and not user controlled for the most part
m
ooh, sorry didn't know that
m
note that for macros you generally need to avoid the upper layers so as to leave room for the grid to connect to the power pins from above
1