Hi, has anyone tried integrating sky130_sram_4kbyt...
# openlane
Hi, has anyone tried integrating sky130_sram_4kbyte_1rw1r_32x1024_8, with their design in the previous shuttle or are planning on using it for this shuttle? We are integrating 4KB sram macros and we are facing issue regarding X bit propagation in rtl simulation. We are using inverted clock and the emulation is passing on xilinx FPGA for the Openram behavioral model. Is inverted clock an issue for the X bit propagation in actual macro? @User https://github.com/merledu/azadi_apr/blob/main/Verification/azadi_soc_top.lvs.powered.v @User @User @User @User @User
@Matt Venn have u used openRAM macro in your design?
No, I haven't got very far with it. I think the new blocks work with openlane, but DRC will still fail because we lack a way to tell openlane to ignore waived DRC.
@Matt Venn even in the macro? as macro can be differentiated with other design in openlane.
@ALI AHMED OpenLane needs a way to use the LEF for memory DRC because it uses core memory rules which will fail normal DRC checks
I'm not sure what the status of this is
@Aireen Amir Jalal