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Erik van Zijst

06/07/2021, 12:03 AM
is there a way to provide values for ``define`'s used in the verilog files from config.tcl? I have a project that uses different values for some defines based on the target (Openlane vs FPGA vs simulation)
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Kevin Dai

06/07/2021, 12:42 AM
I'm not sure how to pass arguments to yosys during synthesis however you can just include a .v file containing all the defines. Seems like that's what caravel does: https://github.com/efabless/caravel/blob/master/openlane/mgmt_core/config.tcl#L55
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Erik van Zijst

06/07/2021, 12:43 AM
Oh yeah interesting. Is the order in which the files get loaded deterministic and fixed then?
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Erik van Zijst

06/07/2021, 1:01 AM
Oh that's awesome. Either of those should work fine. Thanks a bunch!
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Kevin Dai

06/07/2021, 1:01 AM
No problem!