is there a way to provide values for ``define`'s used in the verilog files from config.tcl? I have a project that uses different values for some defines based on the target (Openlane vs FPGA vs simulation)

I'm not sure how to pass arguments to yosys during synthesis however you can just include a .v file containing all the defines. Seems like that's what caravel does: https://github.com/efabless/caravel/blob/master/openlane/mgmt_core/config.tcl#L55

Oh yeah interesting. Is the order in which the files get loaded deterministic and fixed then?

Yes, it seems so https://github.com/The-OpenROAD-Project/OpenLane/blob/master/scripts/synth_top.tcl#L52

Oh that's awesome. Either of those should work fine. Thanks a bunch!

No problem!