Hello, If I have a signal in my RTL which is eithe...
# openlane
w
Hello, If I have a signal in my RTL which is either a constant 0 or 1, how do I tie it to either low or high during synthesis. any ideas here @User Do I pass a command and map it to tie high/low cells etc?
m
what stops you from just assigning it 1 or 0? I don't understand
w
Yes you are right. I was thinking about something else.