I am trying to do digital netlist simulations in OpenLane / Sky130. It seems like the Verilog files for the logic cells are all over the place. Also, the

specify

constructs were somehow moved into separate .specify.v files. How does it all fit together for a netlist simulation, especially with SDF timing annotation?

This might help get you started https://github.com/mattvenn/gate_level_simulation

That is indeed helpful and what I am looking for. But I cannot find this file in my PDK installation:

`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"

Currently checking if I maybe forgot to run some generator for it. Does it contain any

specify

statements on your system (needed for SDF delay annotation)?

your pdk isn't setup correctly I would guess

Thanks! The Verilog files now came out of the open_pdks flow. Unfortunately, specify statements are only present in sky130_fd_io/verilog/sky130_fd_io.v, not the standard cell Verilog files. I guess this has been left out since it is a non-essential part of the flow, but quite important for vector-based power analysis and also helpful for dynamic timing verification.