Hi, I'm trying to test my project with the gate level generated by openlane. By default my project does not work with the gate level. I think that I cause is in the Flip-Flops.
I was looking to the part of my code when I reset some of the Flip-Flops and I found this (Image1).
In theory the output of that Flip-Flop should be 0 not X as shown in the gtkwave (Image 2 is the gate generate by openlane). Any Ideas of the problem? could be that I did not use correct power?
06/16/2021, 9:31 PM
@Ivan Rodriguez Does the VPWR/VGND pin of that flip flop cell have a value when you view it in gtkwave ?
06/17/2021, 6:47 AM
Yes, that was not the issue. The problem was that the clk signal and the reset signal was trigger at the same time, so because was from a non-defined state to high the Flip-Flop does not register the reset. I added extra CLK cycles and seams that now works